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[79.129.180.152]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b8525a94bsm93405385e9.15.2025.08.31.23.53.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Aug 2025 23:53:40 -0700 (PDT) Date: Mon, 01 Sep 2025 09:53:01 +0300 From: Manos Pitsidianakis To: qemu-devel@nongnu.org, Richard Henderson Cc: qemu-arm@nongnu.org Subject: Re: [PATCH 35/61] target/arm: Rename some cpreg to their aarch64 names User-Agent: meli/0.8.12 References: <20250827010453.4059782-1-richard.henderson@linaro.org> <20250827010453.4059782-40-richard.henderson@linaro.org> In-Reply-To: <20250827010453.4059782-40-richard.henderson@linaro.org> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 27 Aug 2025 04:04, Richard Henderson wrote: >Rename those registers which will have FOO_EL12 aliases. > >Signed-off-by: Richard Henderson >--- Reviewed-by: Manos Pitsidianakis > target/arm/helper.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > >diff --git a/target/arm/helper.c b/target/arm/helper.c >index a19406e136..255ca6fdcb 100644 >--- a/target/arm/helper.c >+++ b/target/arm/helper.c >@@ -671,7 +671,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { > */ > { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, > .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, >- { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, >+ { .name = "CPACR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, > .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, > .fgt = FGT_CPACR_EL1, > .nv2_redirect_offset = 0x100 | NV2_REDIR_NV1, >@@ -2012,7 +2012,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { > .resetfn = arm_gt_cntfrq_reset, > }, > /* overall control: mostly access permissions */ >- { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, >+ { .name = "CNTKCTL_EL1", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, > .access = PL1_RW, > .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), >@@ -3071,8 +3071,8 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) > } > > static const ARMCPRegInfo lpae_cp_reginfo[] = { >- /* NOP AMAIR0/1 */ >- { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, >+ /* AMAIR0 is mapped to AMAIR_EL1[31:0] */ >+ { .name = "AMAIR_EL1", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, > .access = PL1_RW, .accessfn = access_tvm_trvm, > .fgt = FGT_AMAIR_EL1, >@@ -4454,9 +4454,9 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) > > static const struct E2HAlias aliases[] = { > { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), >- "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, >+ "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL12" }, > { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), >- "CPACR", "CPTR_EL2", "CPACR_EL12" }, >+ "CPACR_EL1", "CPTR_EL2", "CPACR_EL12" }, > { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), > "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, > { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), >@@ -4478,13 +4478,13 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) > { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), > "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, > { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), >- "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, >+ "AMAIR_EL1", "AMAIR_EL2", "AMAIR_EL12" }, > { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), >- "VBAR", "VBAR_EL2", "VBAR_EL12" }, >+ "VBAR_EL1", "VBAR_EL2", "VBAR_EL12" }, > { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), > "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, > { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), >- "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, >+ "CNTKCTL_EL1", "CNTHCTL_EL2", "CNTKCTL_EL12" }, > > /* > * Note that redirection of ZCR is mentioned in the description >@@ -6999,7 +6999,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) > > if (arm_feature(env, ARM_FEATURE_VBAR)) { > static const ARMCPRegInfo vbar_cp_reginfo[] = { >- { .name = "VBAR", .state = ARM_CP_STATE_BOTH, >+ { .name = "VBAR_EL1", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, > .access = PL1_RW, .writefn = vbar_write, > .accessfn = access_nv1, >@@ -7015,7 +7015,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) > /* Generic registers whose values depend on the implementation */ > { > ARMCPRegInfo sctlr = { >- .name = "SCTLR", .state = ARM_CP_STATE_BOTH, >+ .name = "SCTLR_EL1", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, > .access = PL1_RW, .accessfn = access_tvm_trvm, > .fgt = FGT_SCTLR_EL1, >-- >2.43.0 > >