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[79.129.180.152]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cf270fc3fasm13819030f8f.5.2025.09.01.00.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Sep 2025 00:08:20 -0700 (PDT) Date: Mon, 01 Sep 2025 10:05:22 +0300 From: Manos Pitsidianakis To: qemu-devel@nongnu.org, Richard Henderson Cc: qemu-arm@nongnu.org Subject: Re: [PATCH 43/61] target/arm: Add read_raw_cp_reg128, write_raw_cp_reg128 User-Agent: meli/0.8.12 References: <20250827010453.4059782-1-richard.henderson@linaro.org> <20250827010453.4059782-48-richard.henderson@linaro.org> In-Reply-To: <20250827010453.4059782-48-richard.henderson@linaro.org> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 27 Aug 2025 04:04, Richard Henderson wrote: >Add the functions and update raw_accessors_invalid to match. >Add assertions for !ARM_CP_128BIT in read_raw_cp_reg and >write_raw_cp_reg. > >Signed-off-by: Richard Henderson >--- Reviewed-by: Manos Pitsidianakis > target/arm/cpregs.h | 1 + > target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++---- > 2 files changed, 40 insertions(+), 4 deletions(-) > >diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h >index 0d8c45b60c..bd26a4a260 100644 >--- a/target/arm/cpregs.h >+++ b/target/arm/cpregs.h >@@ -1097,6 +1097,7 @@ static inline bool cp_access_ok(int current_el, > > /* Raw read of a coprocessor register (as needed for migration, etc) */ > uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); >+Int128 read_raw_cp_reg128(CPUARMState *env, const ARMCPRegInfo *ri); > > /* > * Return true if the cp register encoding is in the "feature ID space" as >diff --git a/target/arm/helper.c b/target/arm/helper.c >index 7568b78c49..3efc14da3a 100644 >--- a/target/arm/helper.c >+++ b/target/arm/helper.c >@@ -115,6 +115,7 @@ static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) > > uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) > { >+ assert(!(ri->type & ARM_CP_128BIT)); > /* Raw read of a coprocessor register (as needed for migration, etc). */ > if (ri->type & ARM_CP_CONST) { > return ri->resetvalue; >@@ -130,6 +131,7 @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) > static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t v) > { >+ assert(!(ri->type & ARM_CP_128BIT)); > /* > * Raw write of a coprocessor register (as needed for migration, etc). > * Note that constant registers are treated as write-ignored; the >@@ -147,6 +149,32 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, > } > } > >+Int128 read_raw_cp_reg128(CPUARMState *env, const ARMCPRegInfo *ri) >+{ >+ assert(ri->type & ARM_CP_128BIT); >+ if (ri->raw_read128fn) { >+ return ri->raw_read128fn(env, ri); >+ } else if (ri->read128fn) { >+ return ri->read128fn(env, ri); >+ } else { >+ return raw_read128(env, ri); >+ } >+} >+ >+__attribute__((unused)) >+static void write_raw_cp_reg128(CPUARMState *env, const ARMCPRegInfo *ri, >+ Int128 v) >+{ >+ assert(ri->type & ARM_CP_128BIT); >+ if (ri->raw_write128fn) { >+ ri->raw_write128fn(env, ri, v); >+ } else if (ri->write128fn) { >+ ri->write128fn(env, ri, v); >+ } else { >+ raw_write128(env, ri, v); >+ } >+} >+ > static bool raw_accessors_invalid(const ARMCPRegInfo *ri) > { > /* >@@ -161,12 +189,19 @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri) > * The tests here line up with the conditions in read/write_raw_cp_reg() > * and assertions in raw_read()/raw_write(). > */ >- if ((ri->type & ARM_CP_CONST) || >- ri->fieldoffset || >- ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { >+ if (ri->type & ARM_CP_CONST) { >+ return ri->type & ARM_CP_128BIT; >+ } >+ if (ri->fieldoffset) { > return false; > } >- return true; >+ if (ri->type & ARM_CP_128BIT) { >+ return !((ri->raw_write128fn || ri->write128fn) && >+ (ri->raw_read128fn || ri->read128fn)); >+ } else { >+ return !((ri->raw_writefn || ri->writefn) && >+ (ri->raw_readfn || ri->readfn)); >+ } > } > > bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) >-- >2.43.0 > >