From: "Libo Zhou" <zhlb29@foxmail.com>
To: "Philippe Mathieu-Daud" <philmd@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>
Cc: qemu-devel <qemu-devel@nongnu.org>,
"Aleksandar Markovic" <aleksandar.m.mail@gmail.com>
Subject: Re: illegal hardware instruction during MIPS-I ELF linuxuseremulation
Date: Tue, 24 Sep 2019 22:14:44 +0800 [thread overview]
Message-ID: <tencent_27BC7EC25610890B701F563B@qq.com> (raw)
In-Reply-To: <b4bc1f35-817d-79a0-df4d-07eaa2fdffe5@redhat.com>
> > More updates about this. I just disassembled the unrecognized hex by hand, and figured out that the store word and load word opcodes are not the same as specified in translate.c. While the remaining fields of those unrecognized instructions do match with the source and destination registers.
> What is your compiler/assembler versions (on both machines you used)?
I don't have access to the machine for now and I may not remember the exact version numbers.
The cross compiler I used is a custom compiler based on gcc 4.4.0 (vaguely remember). It generated MIPS-I code that didn't work on QEMU. Specifically some generated opcodes didn't match those in target/mips/translate.c. However, I just checked Wikipedia's MIPS-I opcode table and I think QEMU implements it correctly. The single and double floating point opcode looked a little off for me though, but I didn't use FP ops in my case.
On my own PC I used mipsel-linux-gnu-gcc version 7.4.0. It just worked fine on QEMU.
next prev parent reply other threads:[~2019-09-24 14:42 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-23 16:25 illegal hardware instruction during MIPS-I ELF linux useremulation Libo Zhou
2019-09-23 16:41 ` Peter Maydell
2019-09-24 1:05 ` Libo Zhou
2019-09-24 2:32 ` Libo Zhou
2019-09-24 13:31 ` Libo Zhou
2019-09-24 13:42 ` Philippe Mathieu-Daudé
2019-09-24 14:14 ` Libo Zhou [this message]
2019-09-24 9:36 ` Peter Maydell
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