[PATCH] arm/cpu: revises cortex-r5

[PATCH] arm/cpu: revises cortex-r5

[Yanfeng Liu]

From: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>

This enables generic timer feature for Cortex-R5 so that to support guests
like NuttX RTOS.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
---
 target/arm/tcg/cpu32.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 2ad2182525..5d68d515b4 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -590,9 +590,10 @@ static void cortex_r5_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V7MP);
     set_feature(&cpu->env, ARM_FEATURE_PMSA);
     set_feature(&cpu->env, ARM_FEATURE_PMU);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
     cpu->midr = 0x411fc153; /* r1p3 */
     cpu->isar.id_pfr0 = 0x0131;
-    cpu->isar.id_pfr1 = 0x001;
+    cpu->isar.id_pfr1 = 0x10001;
     cpu->isar.id_dfr0 = 0x010400;
     cpu->id_afr0 = 0x0;
     cpu->isar.id_mmfr0 = 0x0210030;
-- 
2.34.1

Re: [PATCH] arm/cpu: revises cortex-r5

[Philippe Mathieu-Daudé]

Hi,

On 26/1/25 12:43, Yanfeng Liu wrote:
> From: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
> 
> This enables generic timer feature for Cortex-R5 so that to support guests
> like NuttX RTOS.

QEMU aims to model CPU faithful to hardware, than the R5
doesn't has generic timer.

Maybe you want to use the Cortex-R52 instead? I see NuttX supports it:
https://nuttx.apache.org/docs/latest/platforms/arm/fvp-v8r-aarch32/boards/fvp-armv8r-aarch32/index.html

If it works for you, could you add a test for NuttX on Cortex-R52?
See for example tests/functional/test_avr_mega2560.py

Thanks!

Regards,

Phil.

> Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
> ---
>   target/arm/tcg/cpu32.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 2ad2182525..5d68d515b4 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -590,9 +590,10 @@ static void cortex_r5_initfn(Object *obj)
>       set_feature(&cpu->env, ARM_FEATURE_V7MP);
>       set_feature(&cpu->env, ARM_FEATURE_PMSA);
>       set_feature(&cpu->env, ARM_FEATURE_PMU);
> +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
>       cpu->midr = 0x411fc153; /* r1p3 */
>       cpu->isar.id_pfr0 = 0x0131;
> -    cpu->isar.id_pfr1 = 0x001;
> +    cpu->isar.id_pfr1 = 0x10001;
>       cpu->isar.id_dfr0 = 0x010400;
>       cpu->id_afr0 = 0x0;
>       cpu->isar.id_mmfr0 = 0x0210030;

Re: [PATCH] arm/cpu: revises cortex-r5

[Yanfeng Liu]

On Mon, 2025-01-27 at 09:03 +0100, Philippe Mathieu-Daudé wrote:
> Hi,
> 
> On 26/1/25 12:43, Yanfeng Liu wrote:
> > From: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
> > 
> > This enables generic timer feature for Cortex-R5 so that to support guests
> > like NuttX RTOS.
> 
> QEMU aims to model CPU faithful to hardware, than the R5
> doesn't has generic timer.
> 
Okay, I see.

> 
> Maybe you want to use the Cortex-R52 instead? I see NuttX supports it:
> https://nuttx.apache.org/docs/latest/platforms/arm/fvp-v8r-aarch32/boards/fvp-armv8r-aarch32/index.html
> 

Thanks for mentioning this, both commit logs and docs say the r52 support is for
FVP simulator, not for QEMU. Also the MPU memory model support is still missing.

Is it proper to use Cortex-R52 on `virt` board? I am currently using CR5 on
`virt` board to share some code base of armv7-a support.

> If it works for you, could you add a test for NuttX on Cortex-R52?
> See for example tests/functional/test_avr_mega2560.py
> 
> 

I don't know how a FVP guest can help on QEMU testing. But from the sample test
you shared, it seems that a NuttX image URL is needed to create a test case.
That won't be an issue as NuttX images are small and we can have different
images for plain flat memory model, MPU isolated memory model and MMU mapped
memory model if needed. 

If using cortex-r52 on `virt` board is allowed, I may add a NuttX port and share
a binary image URL for a QEMU test case later.

> Thanks!
> 
> Regards,
> 
> Phil.
> 
> > Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
> > ---
> >   target/arm/tcg/cpu32.c | 3 ++-
> >   1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> > index 2ad2182525..5d68d515b4 100644
> > --- a/target/arm/tcg/cpu32.c
> > +++ b/target/arm/tcg/cpu32.c
> > @@ -590,9 +590,10 @@ static void cortex_r5_initfn(Object *obj)
> >       set_feature(&cpu->env, ARM_FEATURE_V7MP);
> >       set_feature(&cpu->env, ARM_FEATURE_PMSA);
> >       set_feature(&cpu->env, ARM_FEATURE_PMU);
> > +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> >       cpu->midr = 0x411fc153; /* r1p3 */
> >       cpu->isar.id_pfr0 = 0x0131;
> > -    cpu->isar.id_pfr1 = 0x001;
> > +    cpu->isar.id_pfr1 = 0x10001;
> >       cpu->isar.id_dfr0 = 0x010400;
> >       cpu->id_afr0 = 0x0;
> >       cpu->isar.id_mmfr0 = 0x0210030;