From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:46093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RSgub-00082u-O9 for qemu-devel@nongnu.org; Mon, 21 Nov 2011 22:20:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RSgua-0003LB-BL for qemu-devel@nongnu.org; Mon, 21 Nov 2011 22:20:45 -0500 Received: from lemon.ertos.nicta.com.au ([203.143.174.143]:34138 helo=lemon.ken.nicta.com.au) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RSguZ-0003L6-PW for qemu-devel@nongnu.org; Mon, 21 Nov 2011 22:20:44 -0500 Date: Tue, 22 Nov 2011 14:20:23 +1100 Message-ID: From: Peter Chubb In-Reply-To: <4ECAD841.1090307@web.de> References: <4ECAD841.1090307@web.de> MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] [ARM] Fix hw_error messages from arm_timer.c List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andreas =?UTF-8?B?RsOkcmJlcg==?= Cc: Peter Maydell , davidm@ok-labs.com, qemu-devel@nongnu.org, Peter Chubb , Paul Brook , Peter Chubb , philipo@ok-labs.com Two of the calls to hw_error() in arm_timer.c contain the wrong function na= me. As suggested by Andreas F=C3=A4rber, use the C99 standard __func__ macro to get the correct name, instead of putting the name directly into the code. Signed-off-by: Peter Chubb --- hw/arm_timer.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) Index: qemu-working/hw/arm_timer.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-working.orig/hw/arm_timer.c 2011-11-22 11:37:33.585457443 +1100 +++ qemu-working/hw/arm_timer.c 2011-11-22 13:10:25.510120391 +1100 @@ -54,21 +54,21 @@ static uint32_t arm_timer_read(void *opa return ptimer_get_count(s->timer); case 2: /* TimerControl */ return s->control; case 4: /* TimerRIS */ return s->int_level; case 5: /* TimerMIS */ if ((s->control & TIMER_CTRL_IE) =3D=3D 0) return 0; return s->int_level; default: - hw_error("arm_timer_read: Bad offset %x\n", (int)offset); + hw_error("%s: Bad offset %x\n", __func__, (int)offset); return 0; } } =20 /* Reset the timer limit after settings have changed. */ static void arm_timer_recalibrate(arm_timer_state *s, int reload) { uint32_t limit; =20 if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) =3D=3D 0= ) { @@ -121,21 +121,21 @@ static void arm_timer_write(void *opaque } break; case 3: /* TimerIntClr */ s->int_level =3D 0; break; case 6: /* TimerBGLoad */ s->limit =3D value; arm_timer_recalibrate(s, 0); break; default: - hw_error("arm_timer_write: Bad offset %x\n", (int)offset); + hw_error("%s: Bad offset %x\n", __func__, (int)offset); } arm_timer_update(s); } =20 static void arm_timer_tick(void *opaque) { arm_timer_state *s =3D (arm_timer_state *)opaque; s->int_level =3D 1; arm_timer_update(s); } @@ -263,35 +263,35 @@ typedef struct { =20 static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset, unsigned size) { icp_pit_state *s =3D (icp_pit_state *)opaque; int n; =20 /* ??? Don't know the PrimeCell ID for this device. */ n =3D offset >> 8; if (n > 2) { - hw_error("sp804_read: Bad timer %d\n", n); + hw_error("%s: Bad timer %d\n", __func__, n); } =20 return arm_timer_read(s->timer[n], offset & 0xff); } =20 static void icp_pit_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { icp_pit_state *s =3D (icp_pit_state *)opaque; int n; =20 n =3D offset >> 8; if (n > 2) { - hw_error("sp804_write: Bad timer %d\n", n); + hw_error("%s: Bad timer %d\n", __func__, n); } =20 arm_timer_write(s->timer[n], offset & 0xff, value); } =20 static const MemoryRegionOps icp_pit_ops =3D { .read =3D icp_pit_read, .write =3D icp_pit_write, .endianness =3D DEVICE_NATIVE_ENDIAN, }; -- Dr Peter Chubb http://www.gelato.unsw.edu.au peterc AT gelato.unsw.edu.au http://www.ertos.nicta.com.au ERTOS within National ICT Australia