QEMU-Riscv Archive on lore.kernel.org
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[PATCH v3 00/11] accel/tcg: Push BQL down into per-target do_interrupt handlers
 2026-09-13  4:00 UTC  (16+ messages)
` [PATCH v3 01/11] target/arm: Call arm*_cpu_do_interrupt directly instead of via TCGCPUOps
` [PATCH v3 03/11] target/i386: Rename fake_do_interrupt to fake_user_exception
` [PATCH v3 04/11] accel/tcg: Document cpu_exec_interrupt() callback contract
` [PATCH v3 05/11] accel/tcg: Document do_interrupt() "
` [PATCH v3 07/11] accel/tcg: Add do_interrupt() wrapper for targets to manage BQL
` [PATCH v3 08/11] target/hexagon: Move to do_interrupt() (BQL acquired internally)
  ` [PATCH v3 02/11] target/s390x: Restrict interrupt handlers to system mode
  ` [PATCH v3 11/11] accel/tcg: Remove do_interrupt_locked() callback

[PATCH v3] target/riscv/tcg: svinval instructions raise virtual instruction
 2026-09-12 11:16 UTC  (2+ messages)

[PATCH v2] target/riscv/tcg: svinval instructions raise virtual instruction
 2026-09-11 20:03 UTC  (3+ messages)

[PATCH 00/28] Mark user creatable devices for secure for virt use case
 2026-09-11 16:50 UTC  (30+ messages)
` [PATCH 01/28] hw: mark secure machines for x86, s390, ppc, arm, loonarch, riscv
` [PATCH 02/28] accel: mark kvm and xen accelerators as secure
` [PATCH 03/28] hw: mark all virtio PCI devices "
` [PATCH 04/28] hw: mark all virtio CCW "
` [PATCH 05/28] hw: mark all vhost devices a secure
` [PATCH 06/28] hw: mark all remaining virtio object types as secure
` [PATCH 07/28] hw/vfio: mark all VFIO object classes "
` [PATCH 08/28] hw/xen: mark all Xen related object types as being secure
` [PATCH 09/28] hw/net: mark e1000, e1000e, IGB, rtl8139 & sPAPR VLAN as secure
` [PATCH 10/28] hw/usb: mark commonly used USB devices/hosts "
` [PATCH 11/28] hw/watchdog: mark some watchdog devices "
` [PATCH 12/28] hw/scsi: mark spapr and vmware SCSI controllers "
` [PATCH 13/28] hw/scsi: mark SCSI disk endpoint devices "
` [PATCH 14/28] hw/ide: mark ICH9 and ide-hd/ide-cd "
` [PATCH 15/28] hw: define most common PCI types "
` [PATCH 16/28] hw/pci-host: mark common x86, ppc, arm and s390 PCI hosts "
` [PATCH 17/28] hw/display: mark bochs, cirrus, qxl, VGA, ramfb "
` [PATCH 18/28] hw/tpm: mark all TPM implementations "
` [PATCH 19/28] hw/misc: mark pvpanic, vmcoreinfo "
` [PATCH 20/28] hw/audio: mark Intel HDA devices & codecs "
` [PATCH 21/28] hw/char: mark common serial / console devicess a secure
` [PATCH 22/28] hw/mem: mark nvdimm, pc-dimm & spapr-nvdimm devices as secure
` [PATCH 23/28] hw/uefi: mark the EFI vars service "
` [PATCH 24/28] hw/acpi: mark erst, vmclock and vmgenid devices "
` [PATCH 25/28] hw: mark KVM clock and RTC "
` [PATCH 26/28] hw: device AMD, Intel and ARM IOMMUs "
` [PATCH 27/28] hw/input: mark PS/2 and PC Keyboard devices "
` [PATCH 28/28] hw/i386: mark vmmouse / vmport "

[PATCH v5 22/62] riscv/virt: convert OnOffAuto properties to QAPI-aware registration
 2026-09-11 16:35 UTC  (4+ messages)
` [PATCH v5 35/62] qom: convert scalar "
` [PATCH v5 53/62] target/riscv: convert PropertyInfo definitions to use qapi_type
` [PATCH v5 56/62] qdev: simplify DEFINE_PROP_ARRAY and remove generic array PropertyInfo

[PATCH 00/10] monitor/hmp: replace MonitorDef with GDB registers
 2026-09-11 15:29 UTC  (12+ messages)
` [PATCH 01/10] hmp: don't crash on invalid register
` [PATCH 02/10] gdbstub: fix next register base after register gaps
` [PATCH 03/10] gdbstub: set feature->base_reg for dynamic features
` [PATCH 04/10] target/i386: expose segment limits via GDB
` [PATCH 05/10] monitor/hmp: add CPUClass::get_pc fallback for HMP $pc
` [PATCH 06/10] target/m68k: expose system registers via GDB
` [PATCH 07/10] target/sparc64: "
` [PATCH 08/10] target/riscv: bypass smstateen check in debugger mode
` [PATCH 09/10] target/riscv: expose register aliases via GDB
` [PATCH 10/10] monitor/hmp: remove legacy MonitorDef infrastructure

[PATCH v4 46/75] qom: convert scalar properties to QAPI-aware registration
 2026-09-11 15:20 UTC  (3+ messages)

[PATCH 00/29] Mark user creatable devices for secure for virt use case
 2026-09-11 14:31 UTC 

[PATCH v4 0/5] target/riscv: fix privilege, PMP, CFI, envcfg checks
 2026-09-11 11:14 UTC  (6+ messages)
` [PATCH v4 1/5] target/riscv: enforce XTheadCmo U-mode privilege checks
` [PATCH v4 3/5] target/riscv: require read permission for HLVX accesses
` [PATCH v4 4/5] target/riscv: prioritize Zicfilp checks for misaligned JALR
` [PATCH v4 5/5] target/riscv: canonicalize reserved CBIE encoding
` [PATCH v4 2/5] target/riscv: decode RV32 XTheadBb th.srri shift amount

[PULL v2 11/75] net/tap: deprecate "no" as special value for script/downscript
 2026-09-11  9:03 UTC  (2+ messages)
` [PULL v2 65/75] hw/hotplug: Constify HotplugHandler

[PATCH 0/6] tests/tcg/riscv64: Add system mode rvv ld/st tests
 2026-09-11  5:49 UTC  (8+ messages)
` [PATCH 1/6] target/riscv: Match PMP entries lying inside the checked range
` [PATCH 2/6] target/riscv: rvv: Probe unit-stride accesses by the first element
` [PATCH 3/6] tests/tcg/riscv64: Add vector masked fault-only-first PMP test
` [PATCH 4/6] tests/tcg/riscv64: Add vector unit-stride "
` [PATCH 5/6] tests/tcg/riscv64: Add vector fault-only-first page probe test
` [PATCH 6/6] tests/tcg/riscv64: Add vector segment PMP region spanning test

[PATCH v3 0/5] target/riscv: fix privilege, PMP, CFI, envcfg checks
 2026-09-11  5:22 UTC  (9+ messages)
` [PATCH v3 1/5] target/riscv: enforce XTheadCmo U-mode privilege checks
` [PATCH v3 5/5] target/riscv: canonicalize reserved CBIE encoding
` [PATCH v3 3/5] target/riscv: require read permission for HLVX accesses
` [PATCH v3 2/5] target/riscv: mask RV32 XTheadBb th.srri shift amount
` [PATCH v3 4/5] target/riscv: prioritize Zicfilp checks for misaligned JALR

[PATCH v2] target/riscv: fix RV32 fixed counter accesses
 2026-09-11  4:44 UTC  (3+ messages)

[PATCH v2 00/14] RISC-V TCG PMU correctness fixes
 2026-09-11  4:43 UTC  (20+ messages)
` [PATCH v2 01/14] target/riscv: Preserve PMU state across event selector writes
` [PATCH v2 02/14] target/riscv: Support multiple counters per PMU event
` [PATCH v2 03/14] target/riscv: Use VM-elapsed sources for fixed PMU events
` [PATCH v2 04/14] target/riscv: Preserve MINH on delegated config reads
` [PATCH v2 05/14] target/riscv: Preserve minstretcfgh on RV32 minstretcfg writes
` [PATCH v2 06/14] target/riscv: Fix RV32 accesses to delegated PMU registers
` [PATCH v2 07/14] target/riscv: Preserve fixed counters across PMU state changes
` [PATCH v2 08/14] target/riscv: Require Sscofpmf for non-fixed event overflow
` [PATCH v2 09/14] target/riscv: Rebuild fixed-event PMU overflow deadlines
` [PATCH v2 10/14] target/riscv: Apply minstret exception accounting to HPM counters
` [PATCH v2 11/14] target/riscv: Process PMU timer expiry on the owner vCPU
` [PATCH v2 12/14] target/riscv: Migrate fixed PMU counter state
` [PATCH v2 13/14] target/riscv: Clear virtualization mode on reset
` [PATCH v2 14/14] target/riscv: Preserve fixed PMU state across reset

[PATCH v2 0/2] linux-user/riscv: fix zicntr gating and reservations
 2026-09-11  1:54 UTC  (3+ messages)
` [PATCH v2 1/2] linux-user/riscv: honor zicntr=false for base counterCSRs
` [PATCH v2 2/2] linux-user/riscv: invalidate reservations after stores

Regular QEMU RISC-V Call
 2026-09-11  0:08 UTC  (3+ messages)

[PATCH] tcg/riscv64: Set vtype before whole-register vector moves
 2026-09-10 22:11 UTC  (3+ messages)

[PULL 21/90] net/tap: deprecate "no" as special value for script/downscript
 2026-09-10 20:15 UTC  (2+ messages)
` [PULL 80/90] hw/hotplug: Constify HotplugHandler

[PATCH v11 0/5] hw/riscv: Server Platform Reference Board
 2026-09-10 17:49 UTC  (12+ messages)
` [PATCH v11 1/5] target/riscv/cpu.c: remove 'bare' condition for .profile
` [PATCH v11 2/5] target/riscv: add riscv-server-ref CPU
` [PATCH v11 3/5] hw/riscv: server platform reference machine
` [PATCH v11 4/5] tests/functional/riscv64: add riscv-server-ref tests
` [PATCH v11 5/5] docs: add riscv-server-ref.rst

[PATCH v2] target/riscv: stop translating after WFI
 2026-09-10 11:45 UTC  (2+ messages)

[PATCH 00/14] RISC-V TCG PMU correctness fixes
 2026-09-10  8:27 UTC  (9+ messages)
` [PATCH 01/14] target/riscv: Preserve PMU state across event selector writes
` [PATCH 02/14] target/riscv: Support multiple counters per PMU event
` [PATCH 03/14] target/riscv: Use VM-elapsed sources for fixed PMU events

[PATCH] target/riscv: stop translating after WFI
 2026-09-10  0:54 UTC  (3+ messages)

[PATCH] target/riscv/tcg: svinval instructions raise virtual instruction
 2026-09-09 21:29 UTC  (3+ messages)

[PATCH v6 0/6] hw/riscv/virt: Add CXL support to the RISC-V virt machine
 2026-09-09 20:49 UTC  (5+ messages)
` [PATCH v6 1/6] "

[PATCH v9 0/7] riscv: add initial sdext support
 2026-09-09 14:48 UTC  (8+ messages)
` [PATCH v9 1/7] target/riscv: add sdext debug CSRs state
` [PATCH v9 2/7] target/riscv: add sdext Debug Mode helpers
` [PATCH v9 3/7] target/riscv: add dret instruction
` [PATCH v9 4/7] target/riscv: add sdext enter Debug Mode on ebreak
` [PATCH v9 5/7] target/riscv: add sdext single-step support
` [PATCH v9 6/7] target/riscv: add sdtrig trigger action=debug mode
` [PATCH v9 7/7] tests/tcg/riscv64: add sdext "not on Debug mode" sigill tests

[PATCH v2] target/riscv: Fix LCOFI interrupt masking in sie/sip/mvip
 2026-09-09 13:42 UTC  (2+ messages)

[PATCH v8 0/7] riscv: add initial sdext support
 2026-09-09 13:32 UTC  (2+ messages)

[PATCH v8 00/11] target/riscv: Implement Smsdid and Smmpt extension
 2026-09-09  7:32 UTC  (3+ messages)
` [PATCH v8 01/11] target/riscv: Add basic definitions and CSRs for SMMPT

[PATCH] target/riscv: fix RV32 fixed counter accesses
 2026-09-09  1:40 UTC  (4+ messages)

[PATCH v10 0/5] hw/riscv: Server Platform Reference Board
 2026-09-08 18:50 UTC  (19+ messages)
` [PATCH v10 1/5] target/riscv/cpu.c: remove 'bare' condition for .profile
` [PATCH v10 2/5] target/riscv: add riscv-server-ref CPU
` [PATCH v10 3/5] hw/riscv: server platform reference machine
` [PATCH v10 4/5] tests/functional/riscv64: add riscv-server-ref tests
` [PATCH v10 5/5] docs: add riscv-server-ref.rst

[GIT PULL 14/15] target/riscv: fix incorrect QAPI types and u8 casting
 2026-09-08 15:06 UTC 

[PATCH 00/50] Aspeed: I2C device models and the Minerva BMC machine
 2026-09-08 10:44 UTC  (14+ messages)
` [PATCH 09/50] hw: ds1338: use the TYPE_DS1338 constant instead of the "ds1338" string
` [PATCH 12/50] hw/rtc: ds1338: parameterise the register map via a device class
` [PATCH 13/50] hw/rtc: ds1338: program the clock from the time registers
` [PATCH 14/50] hw/rtc: ds1338: implement the DS1338 clock-halt bit
` [PATCH 18/50] tests/qtest: ds1338: cover the power-on register defaults
` [PATCH 28/50] tests/qtest: ds1339: cover the 12-hour format
` [PATCH 31/50] tests/qtest: ds1339: cover the migration round trip
` [PATCH 34/50] tests/qtest: ina230: cover voltage injection and power derivation
` [PATCH 35/50] tests/qtest: ina230: cover the ALERT limit functions and CVRF
` [PATCH 36/50] tests/qtest: ina230: cover the injection-property limits
` [PATCH 38/50] tests/qtest: ina230: cover ALERT latch persistence
` [PATCH 46/50] tests/qtest: ina238: cover conversion-ready and alert-latch semantics

[PATCH v10 00/10] riscv: add initial RPMI virt support
 2026-09-08  7:36 UTC  (3+ messages)
` [PATCH v10 01/10] build: add optional librpmi dependency

[PATCH 0/5] target/riscv: fix privilege, PMP, CFI, envcfg checks
 2026-09-08  2:15 UTC  (17+ messages)
` [PATCH 1/5] target/riscv: enforce XTheadCmo U-mode privilege checks
` [PATCH 2/5] target/riscv: mask RV32 XTheadBb th.srri shift amount
` [PATCH 3/5] target/riscv: require read permission for HLVX accesses
` [PATCH 4/5] target/riscv: prioritize Zicfilp checks for misaligned JALR
` [PATCH 5/5] target/riscv: canonicalize reserved CBIE encoding
` [PATCH v2 0/5] target/riscv: fix privilege, PMP, CFI, envcfg checks
  ` [PATCH v2 4/5] target/riscv: prioritize Zicfilp checks for misaligned JALR
  ` [PATCH v2 2/5] target/riscv: mask RV32 XTheadBb th.srri shift amount
  ` [PATCH v2 3/5] target/riscv: require read permission for HLVX accesses
  ` [PATCH v2 5/5] target/riscv: canonicalize reserved CBIE encoding
  ` [PATCH v2 1/5] target/riscv: enforce XTheadCmo U-mode privilege checks

[PATCH v3 0/3] target/riscv: Add experimental Zvabd extension support
 2026-09-08  1:58 UTC  (3+ messages)
` [PATCH v3 1/3] target/riscv: Add support for the Zvabd extension


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