From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
alistair23@gmail.com, chihmin.chao@sifive.com,
palmer@dabbelt.com
Cc: wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH v4 4/4] target/riscv: add vector configure instruction
Date: Tue, 11 Feb 2020 08:56:13 -0800 [thread overview]
Message-ID: <053777e2-7180-5584-cf7f-7876800d9dc8@linaro.org> (raw)
In-Reply-To: <20200210081240.11481-5-zhiwei_liu@c-sky.com>
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
> static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> - target_ulong *cs_base, uint32_t *flags)
> + target_ulong *cs_base, uint32_t *pflags)
> {
> + uint32_t flags = 0;
> + uint32_t vlmax;
> + uint8_t vl_eq_vlmax;
bool.
> +
> *pc = env->pc;
> *cs_base = 0;
> +
> + if (env->misa & RVV) {
> + vlmax = vext_get_vlmax(env_archcpu(env), env->vext.vtype);
> + vl_eq_vlmax = (env->vext.vstart == 0) && (vlmax == env->vext.vl);
You might as well move the variable declarations inside this block.
> +target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> + target_ulong s2)
Indentation.
> +{
> + int vlmax, vl;
> + RISCVCPU *cpu = env_archcpu(env);
> + uint16_t sew = 1 << FIELD_EX64(s2, VTYPE, SEW);
> +
> + if (sew > cpu->cfg.elen) { /* only set vill bit. */
> + env->vext.vtype = FIELD_DP64(0, VTYPE, VILL, 1);
> + env->vext.vl = 0;
> + env->vext.vstart = 0;
> + return 0;
> + }
You're missing checks against EDIV, VILL and the RESERVED field == 0.
> +
> + vlmax = vext_get_vlmax(cpu, s2);
> + if (s1 <= vlmax) {
> + vl = s1;
> + } else {
> + vl = vlmax;
> + }
> + env->vext.vl = vl;
> + env->vext.vtype = s2;
> + env->vext.vstart = 0;
> + return vl;
> +}
>
r~
next prev parent reply other threads:[~2020-02-11 16:56 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-10 8:12 [PATCH v4 0/4]target-riscv: support vector extension part 1 LIU Zhiwei
2020-02-10 8:12 ` [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-02-11 15:53 ` Richard Henderson
2020-02-12 7:17 ` LIU Zhiwei
2020-02-10 8:12 ` [PATCH v4 2/4] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-02-11 15:56 ` Richard Henderson
2020-02-12 7:19 ` LIU Zhiwei
2020-02-18 22:34 ` Alistair Francis
2020-02-19 0:46 ` LIU Zhiwei
2020-02-19 1:05 ` Alistair Francis
2020-02-10 8:12 ` [PATCH v4 3/4] target/riscv: support vector extension csr LIU Zhiwei
2020-02-11 16:11 ` Richard Henderson
2020-02-12 7:23 ` LIU Zhiwei
2020-02-10 8:12 ` [PATCH v4 4/4] target/riscv: add vector configure instruction LIU Zhiwei
2020-02-11 16:56 ` Richard Henderson [this message]
2020-02-12 8:09 ` LIU Zhiwei
2020-02-12 19:28 ` Richard Henderson
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