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[51.195.37.164]) by smtp.gmail.com with ESMTPSA id f27sm8126432pfq.78.2021.09.17.23.28.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Sep 2021 23:28:45 -0700 (PDT) From: Eric Tang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com Subject: [RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions Date: Sat, 18 Sep 2021 14:28:07 +0800 Message-Id: <20210918062816.7546-2-tangxingxin1008@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210918062816.7546-1-tangxingxin1008@gmail.com> References: <20210918062816.7546-1-tangxingxin1008@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=tangxingxin1008@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 18 Sep 2021 04:21:40 -0400 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 18 Sep 2021 06:28:48 -0000 According to spec, these instructions ignore the upper 32 bit of their input and sign-extend their 32 bit output values. Fixed the output's error when their input values greater than 0xffffffff. Signed-off-by: Eric Tang diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index b72e76255c..96b6fcb41d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -484,12 +484,32 @@ static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); } +static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_not_i32(t1, t1); + tcg_gen_shr_i32(t1, t1, t2); + tcg_gen_not_i32(t1, t1); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool trans_srow(DisasContext *ctx, arg_srow *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); ctx->w = true; - return gen_shift(ctx, a, EXT_ZERO, gen_sro); + return gen_shift(ctx, a, EXT_ZERO, gen_srow); } static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) @@ -497,7 +517,7 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVB); ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); + return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_srow); } static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) -- 2.17.1