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[51.195.37.164]) by smtp.gmail.com with ESMTPSA id f27sm8126432pfq.78.2021.09.17.23.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Sep 2021 23:29:10 -0700 (PDT) From: Eric Tang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com Subject: [RFC 05/10] target/riscv: rvb: add crossbar permutation instructions Date: Sat, 18 Sep 2021 14:28:11 +0800 Message-Id: <20210918062816.7546-6-tangxingxin1008@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210918062816.7546-1-tangxingxin1008@gmail.com> References: <20210918062816.7546-1-tangxingxin1008@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=tangxingxin1008@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 18 Sep 2021 04:21:54 -0400 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 18 Sep 2021 06:29:15 -0000 Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 19c64756c5..fa4597b44b 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -205,3 +205,43 @@ target_ulong HELPER(unshflw)(target_ulong rs1, target_ulong rs2) { return do_unshfl(rs1, rs2, 32); } + +static target_ulong do_xperm(target_ulong rs1, + target_ulong rs2, + int sz_log2, + int bits) +{ + target_ulong pos = 0; + target_ulong r = 0; + target_ulong sz = 1LL << sz_log2; + target_ulong mask = (1LL << sz) - 1; + int i; + for (i = 0; i < bits; i += sz) { + pos = ((rs2 >> i) & mask) << sz_log2; + if (pos < bits) { + r |= ((rs1 >> pos) & mask) << i; + } + } + + return r; +} + +target_ulong HELPER(xperm_n)(target_ulong rs1, target_ulong rs2) +{ + return do_xperm(rs1, rs2, 2, TARGET_LONG_BITS); +} + +target_ulong HELPER(xperm_b)(target_ulong rs1, target_ulong rs2) +{ + return do_xperm(rs1, rs2, 3, TARGET_LONG_BITS); +} + +target_ulong HELPER(xperm_h)(target_ulong rs1, target_ulong rs2) +{ + return do_xperm(rs1, rs2, 4, TARGET_LONG_BITS); +} + +target_ulong HELPER(xperm_w)(target_ulong rs1, target_ulong rs2) +{ + return do_xperm(rs1, rs2, 5, TARGET_LONG_BITS); +} diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 015526faf0..ac57982e4f 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -70,6 +70,10 @@ DEF_HELPER_FLAGS_2(shfl, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(unshfl, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(shflw, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(unshflw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(xperm_n, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(xperm_b, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) /* Special functions */ DEF_HELPER_2(csrr, tl, env, int) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e70a38a5c6..60b56dbf95 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -699,6 +699,9 @@ clmulh 0000101 .......... 011 ..... 0110011 @r clmulr 0000101 .......... 010 ..... 0110011 @r shfl 0000100 .......... 001 ..... 0110011 @r unshfl 0000100 .......... 101 ..... 0110011 @r +xperm_n 0010100 .......... 010 ..... 0110011 @r +xperm_b 0010100 .......... 100 ..... 0110011 @r +xperm_h 0010100 .......... 110 ..... 0110011 @r cmix .....11 .......... 001 ..... 0110011 @r4 cmov .....11 .......... 101 ..... 0110011 @r4 @@ -737,6 +740,7 @@ sh3add_uw 0010000 .......... 110 ..... 0111011 @r add_uw 0000100 .......... 000 ..... 0111011 @r shflw 0000100 .......... 001 ..... 0111011 @r unshflw 0000100 .......... 101 ..... 0111011 @r +xperm_w 0010100 .......... 000 ..... 0110011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index cbd48b4c8c..e869d82c8f 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -351,6 +351,24 @@ static bool trans_unshfli(DisasContext *ctx, arg_unshfli *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_helper_unshfl); } +static bool trans_xperm_n(DisasContext *ctx, arg_xperm_n *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_n); +} + +static bool trans_xperm_b(DisasContext *ctx, arg_xperm_b *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_b); +} + +static bool trans_xperm_h(DisasContext *ctx, arg_xperm_h *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_h); +} + #define GEN_TRANS_CLMUL(NAME) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \ { \ @@ -749,3 +767,11 @@ static bool trans_unshflw(DisasContext *ctx, arg_unshflw *a) ctx->w = true; return gen_arith(ctx, a, EXT_ZERO, gen_helper_unshflw); } + +static bool trans_xperm_w(DisasContext *ctx, arg_xperm_w *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + ctx->w = true; + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm_w); +} -- 2.17.1