* [PATCH v9 0/5] support subsets of virtual memory extension
@ 2022-02-04 2:26 Weiwei Li
2022-02-04 2:26 ` [PATCH v9 1/5] target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Weiwei Li @ 2022-02-04 2:26 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, ren_guo, Weiwei Li
This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
Specification:
https://github.com/riscv/virtual-memory/tree/main/specs
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v9
To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'.
This implementation can pass the riscv-tests for rv64ssvnapot.
v9:
* delete cast for PTE bits check
v8:
* rebase on https://lore.kernel.org/qemu-devel/20220131110201.2303275-1-philipp.tomsich@vrull.eu/
* move variables to tops of function
* add ULL for PTE_N and PTE_PMBT
* add mask variable for napot_bits
v7:
* delete definition of PTE_PPN_MASK for TARGET_RISCV32
* make riscv_cpu_sxl works for user mode
* add commit msg for patch 2
v6:
* select ppn mask base on sxl
v5:
* merge patch https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
* relax pte attribute check
v4:
* fix encodings for hinval_vvma and hinval_gvma
* partition inner PTE check into several steps
* improve commit messages to describe changes
v3:
* drop "x-" in exposed properties
v2:
* add extension check for svnapot and svpbmt
Guo Ren (1):
target/riscv: Ignore reserved bits in PTE for RV64
Weiwei Li (4):
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
target/riscv: add support for svnapot extension
target/riscv: add support for svinval extension
target/riscv: add support for svpbmt extension
target/riscv/cpu.c | 4 ++
target/riscv/cpu.h | 16 +++++
target/riscv/cpu_bits.h | 6 ++
target/riscv/cpu_helper.c | 34 +++++++++-
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
7 files changed, 140 insertions(+), 3 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v9 1/5] target/riscv: Ignore reserved bits in PTE for RV64
2022-02-04 2:26 [PATCH v9 0/5] support subsets of virtual memory extension Weiwei Li
@ 2022-02-04 2:26 ` Weiwei Li
2022-02-04 2:26 ` [PATCH v9 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Weiwei Li
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-02-04 2:26 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, ren_guo, Bin Meng
From: Guo Ren <ren_guo@c-sky.com>
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 15 +++++++++++++++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 13 ++++++++++++-
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index aacc997d56..8e7c33c9cb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -324,6 +324,8 @@ struct RISCVCPUConfig {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svnapot;
+ bool ext_svpbmt;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zve32f;
@@ -502,6 +504,19 @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
return 16 << env->xl;
}
+#ifdef TARGET_RISCV32
+#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
+{
+#ifdef CONFIG_USER_ONLY
+ return env->misa_mxl;
+#else
+ return get_field(env->mstatus, MSTATUS64_SXL);
+#endif
+}
+#endif
+
/*
* Encode LMUL to lmul as follows:
* LMUL vlmul lmul
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7c87433645..6ea3944423 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -493,6 +493,9 @@ typedef enum {
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
+/* Page table PPN mask */
+#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL
+
/* Leaf page shift amount */
#define PGSHIFT 12
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 327a2c4f1d..de07aee301 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -454,6 +454,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
bool use_background = false;
+ hwaddr ppn;
+ RISCVCPU *cpu = env_archcpu(env);
/*
* Check if we should use the background registers for the two
@@ -622,7 +624,16 @@ restart:
return TRANSLATE_FAIL;
}
- hwaddr ppn = pte >> PTE_PPN_SHIFT;
+ if (riscv_cpu_sxl(env) == MXL_RV32) {
+ ppn = pte >> PTE_PPN_SHIFT;
+ } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
+ ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
+ } else {
+ ppn = pte >> PTE_PPN_SHIFT;
+ if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
+ return TRANSLATE_FAIL;
+ }
+ }
if (!(pte & PTE_V)) {
/* Invalid PTE */
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v9 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
2022-02-04 2:26 [PATCH v9 0/5] support subsets of virtual memory extension Weiwei Li
2022-02-04 2:26 ` [PATCH v9 1/5] target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li
@ 2022-02-04 2:26 ` Weiwei Li
2022-02-04 2:26 ` [PATCH v9 3/5] target/riscv: add support for svnapot extension Weiwei Li
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-02-04 2:26 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, ren_guo, Weiwei Li
For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index de07aee301..61c3a9a4ad 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -640,6 +640,9 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
+ if (pte & (PTE_D | PTE_A | PTE_U)) {
+ return TRANSLATE_FAIL;
+ }
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v9 3/5] target/riscv: add support for svnapot extension
2022-02-04 2:26 [PATCH v9 0/5] support subsets of virtual memory extension Weiwei Li
2022-02-04 2:26 ` [PATCH v9 1/5] target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li
2022-02-04 2:26 ` [PATCH v9 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Weiwei Li
@ 2022-02-04 2:26 ` Weiwei Li
2022-02-04 2:26 ` [PATCH v9 4/5] target/riscv: add support for svinval extension Weiwei Li
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-02-04 2:26 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, ren_guo, Weiwei Li
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 18 +++++++++++++++---
3 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6df07b8289..cfaccdfc72 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -729,6 +729,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 6ea3944423..7abe9607ff 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -489,6 +489,7 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_N 0x8000000000000000ULL /* NAPOT translation */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 61c3a9a4ad..0adf7bad97 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -456,6 +456,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
bool use_background = false;
hwaddr ppn;
RISCVCPU *cpu = env_archcpu(env);
+ int napot_bits = 0;
+ target_ulong napot_mask;
/*
* Check if we should use the background registers for the two
@@ -640,7 +642,7 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
- if (pte & (PTE_D | PTE_A | PTE_U)) {
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
return TRANSLATE_FAIL;
}
base = ppn << PGSHIFT;
@@ -716,8 +718,18 @@ restart:
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
target_ulong vpn = addr >> PGSHIFT;
- *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
- (addr & ~TARGET_PAGE_MASK);
+
+ if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+ napot_bits = ctzl(ppn) + 1;
+ if ((i != (levels - 1)) || (napot_bits != 4)) {
+ return TRANSLATE_FAIL;
+ }
+ }
+
+ napot_mask = (1 << napot_bits) - 1;
+ *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
+ (vpn & (((target_ulong)1 << ptshift) - 1))
+ ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v9 4/5] target/riscv: add support for svinval extension
2022-02-04 2:26 [PATCH v9 0/5] support subsets of virtual memory extension Weiwei Li
` (2 preceding siblings ...)
2022-02-04 2:26 ` [PATCH v9 3/5] target/riscv: add support for svnapot extension Weiwei Li
@ 2022-02-04 2:26 ` Weiwei Li
2022-02-04 2:26 ` [PATCH v9 5/5] target/riscv: add support for svpbmt extension Weiwei Li
2022-02-10 3:07 ` [PATCH v9 0/5] support subsets of virtual memory extension Alistair Francis
5 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-02-04 2:26 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, ren_guo, Weiwei Li
- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
5 files changed, 85 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cfaccdfc72..4442c4b81d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -729,6 +729,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8e7c33c9cb..5622478eb5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -324,6 +324,7 @@ struct RISCVCPUConfig {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
bool ext_zfh;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5bbedc254c..1d3ff1efe1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -809,3 +809,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** Svinval Standard Extension ***
+sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_w_inval 0001100 00000 00000 000 00000 1110011
+sfence_inval_ir 0001100 00001 00000 000 00000 1110011
+hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
+hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
new file mode 100644
index 0000000000..2682bd969f
--- /dev/null
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the Svinval Standard Instruction Set.
+ *
+ * Copyright (c) 2020-2022 PLCT lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_SVINVAL(ctx) do { \
+ if (!ctx->cfg_ptr->ext_svinval) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as sfence.vma currently */
+ REQUIRE_EXT(ctx, RVS);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.vvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.gvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_gvma_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index eaf5a72c81..84dbfa6340 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -862,6 +862,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_svinval.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v9 5/5] target/riscv: add support for svpbmt extension
2022-02-04 2:26 [PATCH v9 0/5] support subsets of virtual memory extension Weiwei Li
` (3 preceding siblings ...)
2022-02-04 2:26 ` [PATCH v9 4/5] target/riscv: add support for svinval extension Weiwei Li
@ 2022-02-04 2:26 ` Weiwei Li
2022-02-10 3:07 ` [PATCH v9 0/5] support subsets of virtual memory extension Alistair Francis
5 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-02-04 2:26 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, ren_guo, Weiwei Li
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu_bits.h | 2 ++
target/riscv/cpu_helper.c | 4 +++-
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4442c4b81d..e231708ffb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -731,6 +731,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+ DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7abe9607ff..20ab4f4a0d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -489,7 +489,9 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
#define PTE_N 0x8000000000000000ULL /* NAPOT translation */
+#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0adf7bad97..7d805371ed 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -640,9 +640,11 @@ restart:
if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
+ } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+ return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
- if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
return TRANSLATE_FAIL;
}
base = ppn << PGSHIFT;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v9 0/5] support subsets of virtual memory extension
2022-02-04 2:26 [PATCH v9 0/5] support subsets of virtual memory extension Weiwei Li
` (4 preceding siblings ...)
2022-02-04 2:26 ` [PATCH v9 5/5] target/riscv: add support for svpbmt extension Weiwei Li
@ 2022-02-10 3:07 ` Alistair Francis
5 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2022-02-10 3:07 UTC (permalink / raw)
To: Weiwei Li
Cc: Anup Patel, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang,
Wei Wu (吴伟), Guo Ren
On Fri, Feb 4, 2022 at 12:32 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
>
> Specification:
> https://github.com/riscv/virtual-memory/tree/main/specs
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v9
>
> To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'.
>
> This implementation can pass the riscv-tests for rv64ssvnapot.
>
> v9:
> * delete cast for PTE bits check
>
> v8:
> * rebase on https://lore.kernel.org/qemu-devel/20220131110201.2303275-1-philipp.tomsich@vrull.eu/
> * move variables to tops of function
> * add ULL for PTE_N and PTE_PMBT
> * add mask variable for napot_bits
>
> v7:
> * delete definition of PTE_PPN_MASK for TARGET_RISCV32
> * make riscv_cpu_sxl works for user mode
> * add commit msg for patch 2
>
> v6:
> * select ppn mask base on sxl
>
> v5:
> * merge patch https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
> * relax pte attribute check
>
> v4:
> * fix encodings for hinval_vvma and hinval_gvma
> * partition inner PTE check into several steps
> * improve commit messages to describe changes
>
> v3:
> * drop "x-" in exposed properties
>
> v2:
> * add extension check for svnapot and svpbmt
>
> Guo Ren (1):
> target/riscv: Ignore reserved bits in PTE for RV64
>
> Weiwei Li (4):
> target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
> target/riscv: add support for svnapot extension
> target/riscv: add support for svinval extension
> target/riscv: add support for svpbmt extension
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.c | 4 ++
> target/riscv/cpu.h | 16 +++++
> target/riscv/cpu_bits.h | 6 ++
> target/riscv/cpu_helper.c | 34 +++++++++-
> target/riscv/insn32.decode | 7 ++
> target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 7 files changed, 140 insertions(+), 3 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-02-10 3:08 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-02-04 2:26 [PATCH v9 0/5] support subsets of virtual memory extension Weiwei Li
2022-02-04 2:26 ` [PATCH v9 1/5] target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li
2022-02-04 2:26 ` [PATCH v9 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Weiwei Li
2022-02-04 2:26 ` [PATCH v9 3/5] target/riscv: add support for svnapot extension Weiwei Li
2022-02-04 2:26 ` [PATCH v9 4/5] target/riscv: add support for svinval extension Weiwei Li
2022-02-04 2:26 ` [PATCH v9 5/5] target/riscv: add support for svpbmt extension Weiwei Li
2022-02-10 3:07 ` [PATCH v9 0/5] support subsets of virtual memory extension Alistair Francis
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