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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fb72facf9sm28220004f8f.13.2025.10.01.08.07.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 01 Oct 2025 08:07:02 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Pierrick Bouvier , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand , Ilya Leoshkevich , Thomas Huth Subject: [PATCH 18/22] target/s390x: Get cpu first addr space with cpu_get_address_space() Date: Wed, 1 Oct 2025 17:05:23 +0200 Message-ID: <20251001150529.14122-19-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251001150529.14122-1-philmd@linaro.org> References: <20251001150529.14122-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org In order to remove the convenient CPUState::as field, access the vcpu first address space using the cpu_get_address_space() helper. Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/cpu-system.c | 4 +++- target/s390x/mmu_helper.c | 9 +++++---- target/s390x/tcg/excp_helper.c | 10 ++++++---- target/s390x/tcg/mem_helper.c | 6 ++++-- 4 files changed, 18 insertions(+), 11 deletions(-) diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index f3a9ffb2a27..948dd7bc133 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -63,7 +63,9 @@ static void s390_cpu_load_normal(CPUState *s) uint64_t spsw; if (!s390_is_pv()) { - spsw = ldq_phys(s->as, 0); + AddressSpace *as = cpu_get_address_space(s, 0); + + spsw = ldq_phys(as, 0); cpu->env.psw.mask = spsw & PSW_MASK_SHORT_CTRL; /* * Invert short psw indication, so SIE will report a specification diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 4e2f31dc763..358d5463a0a 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -42,9 +42,10 @@ static void trigger_access_exception(CPUS390XState *env, uint32_t type, if (kvm_enabled()) { kvm_s390_access_exception(cpu, type, tec); } else { - CPUState *cs = env_cpu(env); if (type != PGM_ADDRESSING) { - stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); + AddressSpace *as = cpu_get_address_space(env_cpu(env), 0); + + stq_phys(as, env->psa + offsetof(LowCore, trans_exc_code), tec); } trigger_pgm_exception(env, type); } @@ -106,7 +107,7 @@ bool mmu_absolute_addr_valid(target_ulong addr, bool is_write) static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr, uint64_t *entry) { - CPUState *cs = env_cpu(env); + AddressSpace *as = cpu_get_address_space(env_cpu(env), 0); /* * According to the PoP, these table addresses are "unpredictably real @@ -115,7 +116,7 @@ static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr, * * We treat them as absolute addresses and don't wrap them. */ - if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED, + if (unlikely(address_space_read(as, gaddr, MEMTXATTRS_UNSPECIFIED, entry, sizeof(*entry)) != MEMTX_OK)) { return false; diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 4c7faeee82b..1db159be131 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -53,7 +53,7 @@ G_NORETURN void tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc, g_assert(dxc <= 0xff); #if !defined(CONFIG_USER_ONLY) /* Store the DXC into the lowcore */ - stl_phys(env_cpu(env)->as, + stl_phys(cpu_get_address_space(env_cpu(env), 0), env->psa + offsetof(LowCore, data_exc_code), dxc); #endif @@ -70,7 +70,7 @@ G_NORETURN void tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc, g_assert(vxc <= 0xff); #if !defined(CONFIG_USER_ONLY) /* Always store the VXC into the lowcore, without AFP it is undefined */ - stl_phys(env_cpu(env)->as, + stl_phys(cpu_get_address_space(env_cpu(env), 0), env->psa + offsetof(LowCore, data_exc_code), vxc); #endif @@ -639,10 +639,12 @@ void monitor_event(CPUS390XState *env, uint64_t monitor_code, uint8_t monitor_class, uintptr_t ra) { + AddressSpace *as = cpu_get_address_space(env_cpu(env), 0); + /* Store the Monitor Code and the Monitor Class Number into the lowcore */ - stq_phys(env_cpu(env)->as, + stq_phys(as, env->psa + offsetof(LowCore, monitor_code), monitor_code); - stw_phys(env_cpu(env)->as, + stw_phys(as, env->psa + offsetof(LowCore, mon_class_num), monitor_class); tcg_s390_program_interrupt(env, PGM_MONITOR, ra); diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index f1acb1618f7..962f31d4cdb 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -957,12 +957,14 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, uint32_t r1, uint32_t r2) return 0; /* data moved */ inject_exc: #if !defined(CONFIG_USER_ONLY) + AddressSpace *as = cpu_get_address_space(env_cpu(env), 0); + if (exc != PGM_ADDRESSING) { - stq_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, trans_exc_code), + stq_phys(as, env->psa + offsetof(LowCore, trans_exc_code), env->tlb_fill_tec); } if (exc == PGM_PAGE_TRANS) { - stb_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, op_access_id), + stb_phys(as, env->psa + offsetof(LowCore, op_access_id), r1 << 4 | r2); } #endif -- 2.51.0