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Iglesias" , Aurelien Jarno , Richard Henderson , Thomas Huth , Max Filippov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Michael Rolnik , Song Gao , qemu-riscv@nongnu.org, Aleksandar Rikalo , Julian Ganz Subject: [PATCH 19/35] target/mips: call plugin trap callbacks Date: Mon, 27 Oct 2025 11:03:26 +0000 Message-ID: <20251027110344.2289945-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251027110344.2289945-1-alex.bennee@linaro.org> References: <20251027110344.2289945-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org From: Julian Ganz We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for MIPS targets. We consider the exceptions NMI and EXT_INTERRUPT to be asynchronous interrupts rather than exceptions. Reviewed-by: Richard Henderson Acked-by: Philippe Mathieu-Daudé Signed-off-by: Julian Ganz Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée --- target/mips/tcg/system/tlb_helper.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c index 1e8901556d6..566924b079e 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "qemu/bitops.h" +#include "qemu/plugin.h" #include "cpu.h" #include "internal.h" @@ -1034,6 +1035,7 @@ void mips_cpu_do_interrupt(CPUState *cs) bool update_badinstr = 0; target_ulong offset; int cause = -1; + uint64_t last_pc = env->active_tc.PC; if (qemu_loglevel_mask(CPU_LOG_INT) && cs->exception_index != EXCP_EXT_INTERRUPT) { @@ -1052,6 +1054,7 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index = EXCP_NONE; mips_semihosting(env); env->active_tc.PC += env->error_code; + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; case EXCP_DSS: env->CP0_Debug |= 1 << CP0DB_DSS; @@ -1336,6 +1339,14 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, env->CP0_DEPC); } + switch (cs->exception_index) { + case EXCP_NMI: + case EXCP_EXT_INTERRUPT: + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); + break; + default: + qemu_plugin_vcpu_exception_cb(cs, last_pc); + } cs->exception_index = EXCP_NONE; } -- 2.47.3