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Sat, 08 Aug 2026 05:15:39 -0700 (PDT) Received: from localhost.localdomain ([193.145.230.6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-480021e8cd0sm14855995f8f.17.2026.08.08.05.15.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Aug 2026 05:15:39 -0700 (PDT) From: heavenlydev To: Palmer Dabbelt , Alistair Francis Cc: Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Enrique Abma Romero Subject: [PATCH] target/riscv/gdbstub.c: use misa_mxl_max for GPR write width Date: Sat, 8 Aug 2026 14:15:11 +0200 Message-ID: <20260808121511.18088-1-heavenlydev01@gmail.com> X-Mailer: git-send-email 2.50.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=heavenlydev01@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 08 Aug 2026 09:16:25 -0400 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org From: Enrique Abma Romero riscv_cpu_gdb_write_register() decides whether to sign-truncate an incoming GPR value to 32 bits based on env->xl, the hart current XLEN. This is asymmetric with the rest of the gdbstub: both the read path (riscv_cpu_gdb_read_register) and the target description size registers off misa_mxl_max, the maximum XLEN. GDB therefore always exchanges 8-byte register fields for an RV64-max hart, but a write is truncated to its low 32 bits whenever the hart happens to be executing in an RV32 privilege context (env->xl == MXL_RV32, e.g. S/U-mode with SXL/UXL narrowed to 32). The upper 32 bits are silently dropped, so a debugger cannot set the full 64-bit architectural register even though the CPU state and the read path are 64-bit. Key the write width off misa_mxl_max, matching the read path and the advertised register size, so a full-width write is honored regardless of the hart current privilege XLEN. Signed-off-by: Enrique Abma Romero --- target/riscv/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 9abbf5b..9284579 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -89,7 +89,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) const size_t regsize = mcc->def->misa_mxl_max == MXL_RV32 ? 4 : 8; uint64_t tmp = ldn(env, mem_buf, regsize); - if (env->xl < MXL_RV64) { + if (mcc->def->misa_mxl_max < MXL_RV64) { tmp = (int32_t)tmp; } -- 2.39.5