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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id j24sm1344049otn.64.2020.10.01.10.28.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 01 Oct 2020 10:28:25 -0700 (PDT) Subject: Re: [PATCH 3/5] target/riscv: Add H extention state description To: Yifei Jiang , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com References: <20200929020337.1559-1-jiangyifei@huawei.com> <20200929020337.1559-4-jiangyifei@huawei.com> From: Richard Henderson Message-ID: <2e725e26-3952-dbd2-c4aa-d9e933406220@linaro.org> Date: Thu, 1 Oct 2020 12:28:21 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200929020337.1559-4-jiangyifei@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.26, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Oct 2020 17:28:30 -0000 On 9/28/20 9:03 PM, Yifei Jiang wrote: > + VMSTATE_UINTTL(env.vsstatus, RISCVCPU), > + VMSTATE_UINTTL(env.vstvec, RISCVCPU), > + VMSTATE_UINTTL(env.vsscratch, RISCVCPU), > + VMSTATE_UINTTL(env.vsepc, RISCVCPU), > + VMSTATE_UINTTL(env.vscause, RISCVCPU), > + VMSTATE_UINTTL(env.vstval, RISCVCPU), > + VMSTATE_UINTTL(env.vsatp, RISCVCPU), So... if I understand things correctly, this is synthetic state, internal to QEMU. It is generally better to only serialize architectural state, so that if qemu internals are rearranged, it is easy to decide on the correct sequence of operations. It seems like this should be re-generated with a post_load hook, calling some of the code currently in riscv_cpu_swap_hypervisor_regs(). Note that some minor rearrangement would be needed to call that code from this new context. r~