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Mon, 22 Sep 2025 05:43:25 -0700 (PDT) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3f0e28c83d6sm14335469f8f.56.2025.09.22.05.43.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 05:43:24 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 8F2035F7C4; Mon, 22 Sep 2025 13:43:23 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Palmer Dabbelt , Alexandre Iooss , Mahmoud Mandour , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Thomas Huth , Peter Maydell , Alistair Francis , qemu-arm@nongnu.org, Weiwei Li , Pierrick Bouvier , Liu Zhiwei , Richard Henderson Subject: Re: [PATCH 12/25] semihosting/arm-compat-semi: replace target_ulong with vaddr In-Reply-To: <935cfb4b-1990-4ca8-91a2-b9b96b503c42@linaro.org> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Mon, 22 Sep 2025 13:53:26 +0200") References: <20250922093711.2768983-1-alex.bennee@linaro.org> <20250922093711.2768983-13-alex.bennee@linaro.org> <935cfb4b-1990-4ca8-91a2-b9b96b503c42@linaro.org> User-Agent: mu4e 1.12.12; emacs 30.1 Date: Mon, 22 Sep 2025 13:43:23 +0100 Message-ID: <87ldm6odxw.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Philippe Mathieu-Daud=C3=A9 writes: > On 22/9/25 11:36, Alex Benn=C3=A9e wrote: >> From: Pierrick Bouvier >> Reviewed-by: Richard Henderson >> Signed-off-by: Pierrick Bouvier >> Message-ID: <20250822150058.18692-10-pierrick.bouvier@linaro.org> >> Signed-off-by: Alex Benn=C3=A9e >> --- >> semihosting/arm-compat-semi.c | 22 +++++++++++----------- >> 1 file changed, 11 insertions(+), 11 deletions(-) >> diff --git a/semihosting/arm-compat-semi.c >> b/semihosting/arm-compat-semi.c >> index 6725dcf4ba7..29cdab66f73 100644 >> --- a/semihosting/arm-compat-semi.c >> +++ b/semihosting/arm-compat-semi.c >> @@ -123,7 +123,7 @@ static GuestFD console_out_gf; >> */ >> typedef struct LayoutInfo { >> - target_ulong rambase; >> + vaddr rambase; > > This is what the subject describes. Most of the other changes aren't. I was going to say vaddr is functionally a uint64_t but we actually made it a uintptr_t in February. Shall I update to: semihosting/arm-compat-semi: replace target_ulong Replace with vaddr or uint64_t where appropriate ? > >> size_t ramsize; >> hwaddr heapbase; >> hwaddr heaplimit; >> @@ -214,7 +214,7 @@ static LayoutInfo common_semi_find_bases(CPUState *c= s) >> * global, and we assume that the guest takes care of avoiding any rac= es. >> */ >> #ifndef CONFIG_USER_ONLY >> -static target_ulong syscall_err; >> +static uint64_t syscall_err; >> #include "semihosting/uaccess.h" >> #endif >> @@ -260,8 +260,8 @@ static void common_semi_rw_cb(CPUState *cs, uint64_t= ret, int err) >> { >> /* Recover the original length from the third argument. */ >> CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); >> - target_ulong args =3D common_semi_arg(cs, 1); >> - target_ulong arg2; >> + uint64_t args =3D common_semi_arg(cs, 1); >> + uint64_t arg2; >> GET_ARG(2); >> if (err) { >> @@ -300,9 +300,9 @@ static void common_semi_seek_cb(CPUState *cs, uint64= _t ret, int err) >> * is defined by GDB's remote protocol and is not target-specific.) >> * We put this on the guest's stack just below SP. >> */ >> -static target_ulong common_semi_flen_buf(CPUState *cs) >> +static uint64_t common_semi_flen_buf(CPUState *cs) >> { >> - target_ulong sp =3D common_semi_stack_bottom(cs); >> + vaddr sp =3D common_semi_stack_bottom(cs); >> return sp - 64; >> } >> @@ -389,9 +389,9 @@ void semihosting_arm_compatible_init(void) >> void do_common_semihosting(CPUState *cs) >> { >> CPUArchState *env =3D cpu_env(cs); >> - target_ulong args; >> - target_ulong arg0, arg1, arg2, arg3; >> - target_ulong ul_ret; >> + uint64_t args; >> + uint64_t arg0, arg1, arg2, arg3; >> + uint64_t ul_ret; >> char * s; >> int nr; >> int64_t elapsed; >> @@ -462,7 +462,7 @@ void do_common_semihosting(CPUState *cs) >> case TARGET_SYS_WRITEC: >> /* >> - * FIXME: the byte to be written is in a target_ulong slot, >> + * FIXME: the byte to be written is in a uint64_t slot, >> * which means this is wrong for a big-endian guest. >> */ >> semihost_sys_write_gf(cs, common_semi_dead_cb, >> @@ -688,7 +688,7 @@ void do_common_semihosting(CPUState *cs) >> case TARGET_SYS_HEAPINFO: >> { >> - target_ulong retvals[4]; >> + uint64_t retvals[4]; >> int i; >> #ifdef CONFIG_USER_ONLY >> TaskState *ts =3D get_task_state(cs); --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro