messages from 2021-08-31 02:30:33 to 2021-09-03 19:31:18 UTC [more...]
[PATCH v3 00/30] accel: Move has_work() from SysemuCPUOps to AccelOpsClass
2021-09-03 19:31 UTC (28+ messages)
` [PATCH v3 01/30] accel/tcg: Restrict cpu_handle_halt() to sysemu
` [PATCH v3 02/30] hw/core: Restrict cpu_has_work() "
` [PATCH v3 03/30] hw/core: Un-inline cpu_has_work()
` [PATCH v3 04/30] sysemu: Introduce AccelOpsClass::has_work()
` [PATCH v3 05/30] accel/kvm: Implement AccelOpsClass::has_work()
` [PATCH v3 06/30] accel/whpx: "
` [PATCH v3 07/30] accel/tcg: Implement AccelOpsClass::has_work() as stub
` [PATCH v3 08/30] target/alpha: Restrict has_work() handler to sysemu and TCG
` [PATCH v3 09/30] target/arm: "
` [PATCH v3 10/30] target/avr: "
` [PATCH v3 11/30] target/cris: "
` [PATCH v3 12/30] target/hexagon: Remove unused has_work() handler
` [PATCH v3 13/30] target/hppa: Restrict has_work() handler to sysemu and TCG
` [PATCH v3 14/30] target/i386: "
` [PATCH v3 15/30] target/m68k: "
` [PATCH v3 16/30] target/microblaze: "
` [PATCH v3 17/30] target/mips: "
` [PATCH v3 18/30] target/nios2: "
` [PATCH v3 19/30] target/openrisc: "
` [PATCH v3 20/30] target/ppc: "
` [PATCH v3 21/30] target/ppc: Introduce PowerPCCPUClass::has_work()
` [PATCH v3 22/30] target/ppc: Simplify has_work() handlers
` [PATCH v3 23/30] target/riscv: Restrict has_work() handler to sysemu and TCG
` [PATCH v3 24/30] target/rx: "
[PATCH 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
2021-09-03 19:27 UTC (72+ messages)
` [PATCH 01/24] target/xtensa: Restrict do_transaction_failed() "
` [PATCH 02/24] target/i386: Restrict sysemu-only fpu_helper helpers
` [PATCH 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry
` [RFC PATCH 04/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_exception
` [PATCH 05/24] accel/tcg: Assert most of cpu_handle_interrupt() is sysemu-specific
` [PATCH 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu
` [PATCH 07/24] target/arm: "
` [PATCH 08/24] target/avr: "
` [PATCH 09/24] target/cris: "
` [PATCH 10/24] target/hppa: "
` [PATCH 11/24] target/i386: "
` [PATCH 12/24] target/m68k: "
` [PATCH 13/24] target/microblaze: "
` [PATCH 14/24] target/mips: "
` [PATCH 15/24] target/nios2: "
` [PATCH 16/24] target/openrisc: "
` [PATCH 17/24] target/ppc: "
` [PATCH 18/24] target/riscv: "
` [PATCH 19/24] target/sh4: "
` [PATCH 20/24] target/sparc: "
` [PATCH 21/24] target/rx: "
` [PATCH 22/24] target/xtensa: "
` [PATCH 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() "
` [PATCH 24/24] user: Remove cpu_get_pic_interrupt() stubs
[PATCH v1 0/2] RISC-V: Populate mtval and stval
2021-09-03 17:05 UTC (5+ messages)
` [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction
` [PATCH v1 2/2] target/riscv: Set mtval and stval support
[PATCH v1 1/3] hw/riscv: virt: Don't use a macro for the PLIC configuration
2021-09-03 11:21 UTC (5+ messages)
` [PATCH v1 2/3] hw/riscv/sifive_u: Use the PLIC config helper function
` [PATCH v1 3/3] hw/riscv/microchip_pfsoc: "
[PATCH v2 00/22] QEMU RISC-V AIA support
2021-09-03 3:32 UTC (24+ messages)
` [PATCH v2 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
` [PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
` [PATCH v2 03/22] target/riscv: Implement hgeie and hgeip CSRs
` [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts
` [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
` [PATCH v2 06/22] target/riscv: Add AIA cpu feature
` [PATCH v2 07/22] target/riscv: Add defines for AIA CSRs
` [PATCH v2 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
` [PATCH v2 09/22] target/riscv: Implement AIA local interrupt priorities
` [PATCH v2 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
` [PATCH v2 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
` [PATCH v2 12/22] target/riscv: Implement AIA interrupt filtering CSRs
` [PATCH v2 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
` [PATCH v2 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
` [PATCH v2 15/22] target/riscv: Implement AIA IMSIC interface CSRs
` [PATCH v2 16/22] hw/riscv: virt: Use AIA INTC compatible string when available
` [PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART
` [PATCH v2 18/22] hw/intc: Add RISC-V AIA APLIC device emulation
` [PATCH v2 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine
` [PATCH v2 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation
` [PATCH v2 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
` [PATCH v2 22/22] docs/system: riscv: Document AIA options for "
[PATCH v2 0/2] Add the SiFive PWM device
2021-09-02 23:25 UTC (3+ messages)
` [PATCH v2 1/2] hw/timer: Add SiFive PWM support
` [PATCH v2 2/2] sifive_u: Connect the SiFive PWM device
[PATCH 00/29] [RFC] build more i386 tcg code modular
2021-09-02 13:09 UTC (34+ messages)
` [PATCH 01/29] build: temporarily disable modular tcg
` [PATCH 02/29] plugins: register qemu_plugin_opts using opts_init()
` [PATCH 03/29] tcg/module: move hmp.c to module
` [PATCH 04/29] tcg/module: move cputlb.c "
` [PATCH 05/29] tcg/module: move tcg_ss to module [accel/tcg]
` [PATCH 06/29] tcg/module: move tcg_ss to module [tcg]
` [PATCH 07/29] tcg/module: move files to module [target/i386/tcg]
` [PATCH 08/29] move cpu-exec-common.c from tcg module to core qemu [accel/tcg]
` [PATCH 09/29] tcg/module: add tcg-module.[ch] infrastructure
` [PATCH 10/29] tcg_funcs: Add tlb_flush to TCGModuleOps
` [PATCH 11/29] tcg_funcs: Add tlb_flush_page "
` [PATCH 12/29] tcg_funcs: Add tlb_reset_dirty "
` [PATCH 13/29] tcg_funcs: Add tlb_plugin_lookup "
` [PATCH 14/29] tcg_funcs:Add tcg_exec_{realizefn, unrealizefn} "
` [PATCH 15/29] tcg_funcs: Add tb_flush "
` [PATCH 16/29] tcg: use tb_page_addr_t for tb_invalidate_phys_range()
` [PATCH 17/29] tcg: drop tb_invalidate_phys_page_range()
` [PATCH 18/29] tcg_funcs: Add tb_invalidate_phys_range to TCGModuleOps
` [PATCH 19/29] tcg_funcs: Add tb_check_watchpoint "
` [PATCH 20/29] tcg_funcs: Add cpu_restore_state "
` [PATCH 21/29] tcg_funcs: Add curr_cflags "
` [PATCH 22/29] tcg_i386_funcs: Add update_fp_status to TCGI386ModuleOps
` [PATCH 23/29] tcg_i386_funcs: Add update_mxcsr_status "
` [PATCH 24/29] tcg_i386_funcs: Add update_mxcsr_from_sse_status "
` [PATCH 25/29] tcg_i386_funcs: Add x86_register_ferr_irq "
` [PATCH 26/29] tcg_i386_funcs: Add cpu_set_ignne "
` [PATCH 27/29] tcg_i386_funcs: Add cpu_x86_update_dr7 "
` [PATCH 28/29] tcg_i386_funcs: Add cpu_cc_compute_all "
` [PATCH 29/29] Revert "build: temporarily disable modular tcg"
[PATCH v1 1/1] target/riscv: Update the ePMP CSR address
2021-09-02 5:19 UTC (3+ messages)
[PATCH] target/riscv: Fix satp write
2021-09-02 2:49 UTC (7+ messages)
[RFC PATCH 0/2] riscv: Adding custom CSR related Kconfig options
2021-09-02 2:25 UTC (2+ messages)
[PATCH 0/8] RISC V partial support for 128-bit architecture
2021-08-31 17:25 UTC (4+ messages)
[PATCH 1/8] target/riscv: Settings for 128-bit extension support
2021-08-31 16:20 UTC (17+ messages)
` [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions
` [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions
` [PATCH 6/8] target/riscv: Support of compiler's 128-bit integer types
` [PATCH 7/8] target/riscv: 128-bit support for some csrs
[PATCH v4 0/4] QEMU RISC-V ACLINT Support
2021-08-31 11:06 UTC (5+ messages)
` [PATCH v4 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources
` [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
` [PATCH v4 3/4] hw/riscv: virt: Re-factor FDT generation
` [PATCH v4 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine
[PATCH v3 0/4] QEMU RISC-V ACLINT Support
2021-08-31 8:45 UTC (4+ messages)
` [PATCH v3 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
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