messages from 2021-10-23 08:48:38 to 2021-10-29 19:46:24 UTC [more...]
[PATCH v9 00/76] support vector extension v1.0
2021-10-29 19:46 UTC (78+ messages)
` [PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support
` [PATCH v9 02/76] target/riscv: Use FIELD_EX32() to extract wd field
` [PATCH v9 03/76] target/riscv: rvv-1.0: add mstatus VS field
` [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
` [PATCH v9 05/76] target/riscv: rvv-1.0: add sstatus VS field
` [PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field
` [PATCH v9 07/76] target/riscv: rvv-1.0: add translation-time vector context status
` [PATCH v9 08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
` [PATCH v9 09/76] target/riscv: rvv-1.0: add vcsr register
` [PATCH v9 10/76] target/riscv: rvv-1.0: add vlenb register
` [PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
` [PATCH v9 12/76] target/riscv: rvv-1.0: remove MLEN calculations
` [PATCH v9 13/76] target/riscv: rvv-1.0: add fractional LMUL
` [PATCH v9 14/76] target/riscv: rvv-1.0: add VMA and VTA
` [PATCH v9 15/76] target/riscv: rvv-1.0: update check functions
` [PATCH v9 16/76] target/riscv: introduce more imm value modes in translator functions
` [PATCH v9 17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function
` [PATCH v9 18/76] target/riscv: rvv-1.0: remove amo operations instructions
` [PATCH v9 19/76] target/riscv: rvv-1.0: configure instructions
` [PATCH v9 20/76] target/riscv: rvv-1.0: stride load and store instructions
` [PATCH v9 21/76] target/riscv: rvv-1.0: index "
` [PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
` [PATCH v9 23/76] target/riscv: rvv-1.0: fault-only-first unit stride load
` [PATCH v9 24/76] target/riscv: rvv-1.0: load/store whole register instructions
` [PATCH v9 25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
` [PATCH v9 26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
` [PATCH v9 27/76] target/riscv: rvv-1.0: floating-point square-root instruction
` [PATCH v9 28/76] target/riscv: rvv-1.0: floating-point classify instructions
` [PATCH v9 29/76] target/riscv: rvv-1.0: count population in mask instruction
` [PATCH v9 30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction
` [PATCH v9 31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions
` [PATCH v9 32/76] target/riscv: rvv-1.0: iota instruction
` [PATCH v9 33/76] target/riscv: rvv-1.0: element index instruction
` [PATCH v9 34/76] target/riscv: rvv-1.0: allow load element with sign-extended
` [PATCH v9 35/76] target/riscv: rvv-1.0: register gather instructions
` [PATCH v9 36/76] target/riscv: rvv-1.0: integer scalar move instructions
` [PATCH v9 37/76] target/riscv: rvv-1.0: floating-point move instruction
` [PATCH v9 38/76] target/riscv: rvv-1.0: floating-point scalar move instructions
` [PATCH v9 39/76] target/riscv: rvv-1.0: whole register "
` [PATCH v9 40/76] target/riscv: rvv-1.0: integer extension instructions
` [PATCH v9 41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
` [PATCH v9 42/76] target/riscv: rvv-1.0: single-width bit shift instructions
` [PATCH v9 43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
` [PATCH v9 44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions
` [PATCH v9 45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions
` [PATCH v9 46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
` [PATCH v9 47/76] target/riscv: rvv-1.0: integer comparison instructions
` [PATCH v9 48/76] target/riscv: rvv-1.0: floating-point compare instructions
` [PATCH v9 49/76] target/riscv: rvv-1.0: mask-register logical instructions
` [PATCH v9 50/76] target/riscv: rvv-1.0: slide instructions
` [PATCH v9 51/76] target/riscv: rvv-1.0: floating-point "
` [PATCH v9 52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
` [PATCH v9 53/76] target/riscv: rvv-1.0: single-width floating-point reduction
` [PATCH v9 54/76] target/riscv: rvv-1.0: widening floating-point reduction instructions
` [PATCH v9 55/76] target/riscv: rvv-1.0: single-width scaling shift instructions
` [PATCH v9 56/76] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
` [PATCH v9 57/76] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
` [PATCH v9 58/76] target/riscv: rvv-1.0: remove integer extract instruction
` [PATCH v9 59/76] target/riscv: rvv-1.0: floating-point min/max instructions
` [PATCH v9 60/76] target/riscv: introduce floating-point rounding mode enum
` [PATCH v9 61/76] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
` [PATCH v9 62/76] target/riscv: rvv-1.0: widening floating-point/integer type-convert
` [PATCH v9 63/76] target/riscv: add "set round to odd" rounding mode helper function
` [PATCH v9 64/76] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
` [PATCH v9 65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
` [PATCH v9 66/76] target/riscv: rvv-1.0: implement vstart CSR
` [PATCH v9 67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
` [PATCH v9 68/76] target/riscv: gdb: support vector registers for rv64 & rv32
` [PATCH v9 69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
` [PATCH v9 70/76] target/riscv: rvv-1.0: floating-point reciprocal "
` [PATCH v9 71/76] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
` [PATCH v9 72/76] target/riscv: rvv-1.0: add vsetivli instruction
` [PATCH v9 73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
` [PATCH v9 74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
` [PATCH v9 75/76] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
` [PATCH v9 76/76] target/riscv: rvv-1.0: update opivv_vadc_check() comment
[PATCH 0/5] target/riscv: Initial support for native debug feature via M-mode CSRs
2021-10-29 19:41 UTC (10+ messages)
` [PATCH 1/5] target/riscv: Add initial support for native debug
` [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps
` [PATCH 3/5] target/riscv: Add a config option for native debug
` [PATCH 4/5] target/riscv: csr: Hook debug CSR read/write
` [PATCH 5/5] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
[PATCH v2 0/2] mconfigptr support
2021-10-28 2:34 UTC (9+ messages)
` [PATCH v2 1/2] target/riscv: Add priv spec 1.12.0 version check
` [PATCH v2 2/2] target/riscv: csr: Implement mconfigptr CSR
[PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS
2021-10-27 3:24 UTC (4+ messages)
` [PATCH v2 2/2] target/riscv: remove force HS exception
[PATCH v3] target/riscv: fix VS interrupts forwarding to HS
2021-10-26 6:57 UTC (8+ messages)
[PATCH v8 00/78] support vector extension v1.0
2021-10-26 6:55 UTC (25+ messages)
` [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
` [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point slide instructions
` [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
` [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert
` [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function
` [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
` [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
` [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs
` [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
` [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction
` [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
` [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment
[PATCH v4 00/22] QEMU RISC-V AIA support
2021-10-26 6:42 UTC (23+ messages)
` [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
` [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
` [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs
` [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts
` [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
` [PATCH v4 06/22] target/riscv: Add AIA cpu feature
` [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs
` [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
` [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities
` [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
` [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
` [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs
` [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
` [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
` [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs
` [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available
` [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART
` [PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation
` [PATCH v4 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine
` [PATCH v4 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation
` [PATCH v4 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
` [PATCH v4 22/22] docs/system: riscv: Document AIA options for "
[PATCH v3 00/22] QEMU RISC-V AIA support
2021-10-26 5:02 UTC (3+ messages)
` [PATCH v3 22/22] docs/system: riscv: Document AIA options for virt machine
[PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses
2021-10-25 22:33 UTC (3+ messages)
[PATCH v17 0/8] RISC-V Pointer Masking implementation
2021-10-25 22:32 UTC (11+ messages)
` [PATCH v17 1/8] target/riscv: Add J-extension into RISC-V
` [PATCH v17 2/8] target/riscv: Add CSR defines for RISC-V PM extension
` [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v17 4/8] target/riscv: Add J extension state description
` [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs
` [PATCH v17 6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
` [PATCH v17 7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
` [PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on
[PATCH v4 00/17] Adding partial support for 128-bit riscv target
2021-10-25 20:16 UTC (26+ messages)
` [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO
` [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations
` [PATCH v4 03/17] target/riscv: additional macros to check instruction support
` [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers
` [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers
` [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles
` [PATCH v4 07/17] target/riscv: moving some insns close to similar insns
` [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store
` [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions
` [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions
` [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions
` [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions
` [PATCH v4 13/17] target/riscv: support for 128-bit M extension
` [PATCH v4 14/17] target/riscv: adding high part of some csrs
` [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns
` [PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support
` [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns
[ PATCH v3 00/10] Improve PMU support
2021-10-25 19:56 UTC (11+ messages)
` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function
` [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
` [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu
` [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable
` [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR
` [ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents
` [ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation
` [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support
` [ PATCH v3 09/10] target/riscv: Add few cache related PMU events
` [ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree
[PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
2021-10-25 14:58 UTC (5+ messages)
[PATCH v16 0/8] RISC-V Pointer Masking implementation
2021-10-25 5:53 UTC (6+ messages)
` [PATCH v16 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v16 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs
[PATCH v3 00/21] Adding partial support for 128-bit riscv target
2021-10-24 22:49 UTC (4+ messages)
` [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions
[PATCH] tests/tcg: Fix some targets default cross compiler path
2021-10-23 18:07 UTC (3+ messages)
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