messages from 2021-10-29 09:03:55 to 2021-11-11 15:18:54 UTC [more...]
[PATCH v3 00/20] Support UXL filed in xstatus
2021-11-11 15:18 UTC (35+ messages)
` [PATCH v3 01/20] target/riscv: Don't save pc when exception return
` [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN
` [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN
` [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write
` [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen
` [PATCH v3 06/20] target/riscv: Relax debug check for pm write
` [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN
` [PATCH v3 08/20] target/riscv: Create current pm fields in env
` [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base]
` [PATCH v3 10/20] target/riscv: Calculate address according to XLEN
` [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base
` [PATCH v3 12/20] target/riscv: Split out the vill from vtype
` [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE
` [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN
` [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE
` [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN
` [PATCH v3 17/20] target/riscv: Fix check range for first fault only
` [PATCH v3 18/20] target/riscv: Adjust vector address with mask
` [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN
` [PATCH v3 20/20] target/riscv: Enable uxl field write
[PATCH v2 00/14] Support UXL filed in xstatus
2021-11-11 5:04 UTC (34+ messages)
` [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN
` [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN
` [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write
` [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen
` [PATCH v2 05/14] target/riscv: Calculate address according to XLEN
` [PATCH v2 06/14] target/riscv: Adjust vsetvl "
` [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN
` [PATCH v2 08/14] target/riscv: Fix check range for first fault only
` [PATCH v2 09/14] target/riscv: Relax debug check for pm write
` [PATCH v2 10/14] target/riscv: Adjust vector address with mask
` [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN
` [PATCH v2 12/14] target/riscv: Split out the vill from vtype
` [PATCH v2 13/14] target/riscv: Don't save pc when exception return
` [PATCH v2 14/14] target/riscv: Enable uxl field write
[PATCH 00/13] Support UXL filed in xstatus
2021-11-10 3:01 UTC (44+ messages)
` [PATCH 01/13] target/riscv: Sign extend pc for different ol
` [PATCH 02/13] target/riscv: Extend pc for runtime pc write
` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN
` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen
` [PATCH 05/13] target/riscv: Calculate address according to ol
` [PATCH 06/13] target/riscv: Adjust vsetvl "
` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol
` [PATCH 08/13] target/riscv: Fix check range for first fault only
` [PATCH 09/13] target/riscv: Adjust vector address with ol
` [PATCH 10/13] target/riscv: Adjust scalar reg in vector "
` [PATCH 11/13] target/riscv: Switch context in exception return
` [PATCH 12/13] target/riscv: Don't save pc when "
` [PATCH 13/13] target/riscv: Enable uxl field write
[ PATCH v3 00/10] Improve PMU support
2021-11-04 11:49 UTC (16+ messages)
` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function
` [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
` [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu
` [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable
` [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR
[PATCH v4 00/22] QEMU RISC-V AIA support
2021-11-04 4:56 UTC (24+ messages)
` [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
` [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
` [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts
` [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs
` [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback
` [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
` [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
` [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs
` [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs
[PATCH] target/riscv: machine: Sort the .subsections
2021-11-03 21:52 UTC (3+ messages)
[RFC 0/6] support subsets of scalar crypto extension
2021-11-03 7:22 UTC (17+ messages)
` [RFC 1/6] target/riscv: rvk: add flag support for Zbk[bcx]
` [RFC 2/6] target/riscv: rvk: add implementation of instructions for Zbk* - reuse partial instructions of Zbb/Zbc extensions - add brev8 packh, unzip, zip, etc
` [RFC 3/6] target/riscv: rvk: add flag support for Zk/Zkn/Zknd/Zknd/Zkne/Zknh/Zks/Zksed/Zksh/Zkr
` [RFC 4/6] target/riscv: rvk: add implementation of instructions for Zk*
` [RFC 5/6] target/riscv: rvk: add CSR support for Zkr: - add SEED CSR - add USEED, SSEED fields for MSECCFG CSR
` [RFC 6/6] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
[PATCH v2 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
2021-11-03 6:00 UTC (10+ messages)
` [PATCH v2 1/7] target/riscv: Add initial support for native debug
` [PATCH v2 2/7] target/riscv: machine: Add debug state description
` [PATCH v2 3/7] target/riscv: debug: Implement debug related TCGCPUOps
` [PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug
` [PATCH v2 5/7] target/riscv: csr: Hook debug CSR read/write
` [PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on virt and sifive_u CPUs
` [PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
[PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1
2021-11-02 14:07 UTC (2+ messages)
[PATCH v4 00/17] Adding partial support for 128-bit riscv target
2021-11-02 13:22 UTC (19+ messages)
` [PATCH v4 03/17] target/riscv: additional macros to check instruction support
` [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles
` [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store
` [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions
` [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions
` [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions
` [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions
` [PATCH v4 13/17] target/riscv: support for 128-bit M extension
` [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns
[PATCH v9 00/76] support vector extension v1.0
2021-11-01 6:45 UTC (16+ messages)
` [PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support
` [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
` [PATCH v9 66/76] target/riscv: rvv-1.0: implement vstart CSR
` [PATCH v9 67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
` [PATCH v9 68/76] target/riscv: gdb: support vector registers for rv64 & rv32
` [PATCH v9 69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
` [PATCH v9 70/76] target/riscv: rvv-1.0: floating-point reciprocal "
` [PATCH v9 71/76] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
` [PATCH v9 72/76] target/riscv: rvv-1.0: add vsetivli instruction
` [PATCH v9 73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
` [PATCH v9 74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
` [PATCH v9 75/76] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
` [PATCH v9 76/76] target/riscv: rvv-1.0: update opivv_vadc_check() comment
[PATCH 0/5] target/riscv: Initial support for native debug feature via M-mode CSRs
2021-10-29 19:41 UTC (10+ messages)
` [PATCH 1/5] target/riscv: Add initial support for native debug
` [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps
` [PATCH 3/5] target/riscv: Add a config option for native debug
` [PATCH 4/5] target/riscv: csr: Hook debug CSR read/write
` [PATCH 5/5] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
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