messages from 2024-09-12 23:55:03 to 2024-10-02 00:06:42 UTC [more...]
[PATCH for-9.2 v6 00/12] riscv: QEMU RISC-V IOMMU Support
2024-10-02 0:05 UTC (8+ messages)
` [PATCH for-9.2 v6 03/12] hw/riscv: add RISC-V IOMMU base emulation
[RFC 0/1] target/riscv: use a simplified loop to emulate rvv loads/stores only in user mode
2024-10-01 16:36 UTC (3+ messages)
` [RFC 1/1] "
[PATCH] hw/char/riscv_htif: Fix htif_mm_write that causes infinite loop in ACT
2024-10-01 6:12 UTC (2+ messages)
[PATCH v3 00/14] macOS PV Graphics and new vmapple machine type
2024-10-01 9:40 UTC (17+ messages)
` [PATCH v3 01/14] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support
` [PATCH v3 02/14] hw/display/apple-gfx: Adds PCI implementation
` [PATCH v3 03/14] ui/cocoa: Adds non-app runloop on main thread mode
` [PATCH v3 04/14] hw/display/apple-gfx: Adds configurable mode list
` [PATCH v3 05/14] MAINTAINERS: Add myself as maintainer for apple-gfx, reviewer for HVF
` [PATCH v3 06/14] hw: Add vmapple subdir
` [PATCH v3 07/14] hw/misc/pvpanic: Add MMIO interface
` [PATCH v3 08/14] hvf: arm: Ignore writes to CNTP_CTL_EL0
` [PATCH v3 09/14] gpex: Allow more than 4 legacy IRQs
` [PATCH v3 10/14] hw/vmapple/aes: Introduce aes engine
` [PATCH v3 11/14] hw/vmapple/bdif: Introduce vmapple backdoor interface
` [PATCH v3 12/14] hw/vmapple/cfg: Introduce vmapple cfg region
` [PATCH v3 13/14] hw/vmapple/virtio-blk: Add support for apple virtio-blk
` [PATCH v3 14/14] hw/vmapple/vmapple: Add vmapple machine type
[PATCH] target/riscv: Set vtype.vill on CPU reset
2024-09-30 16:52 UTC
[PATCH] hw/riscv/spike: Replace tswap64() by ldq_endian_p()
2024-09-30 12:48 UTC
[PATCH] hw/char/riscv_htif: Fix htif_mm_write that causes infinite loop in ACT
2024-09-27 7:00 UTC
[PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU
2024-09-26 21:55 UTC (11+ messages)
` [PATCH v7 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
` [PATCH v7 2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
` [PATCH v7 3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
` [PATCH v7 4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64
` [PATCH v7 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
` [PATCH v7 6/8] target/riscv: Enable RV32 CPU support "
` [PATCH v7 7/8] target/riscv: Add max32 CPU for "
` [PATCH v7 8/8] tests/avocado: Boot Linux for RV32 cpu on "
[PATCH] target/riscv/csr.c: Fix an access to VXSAT
2024-09-26 8:39 UTC (3+ messages)
` [PATCH v2] "
[PATCH] hw/riscv/virt: Comment absence of #msi-cells
2024-09-25 17:53 UTC (2+ messages)
[PATCH v2 0/8] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions
2024-09-25 11:58 UTC (9+ messages)
` [PATCH v2 1/8] target/riscv: Add Ssdbltrp CSRs handling
` [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior
` [PATCH v2 3/8] target/riscv: Implement Ssdbltrp exception handling
` [PATCH v2 4/8] target/riscv: Add Ssdbltrp ISA extension enable switch
` [PATCH v2 5/8] target/riscv: Add Smdbltrp CSRs handling
` [PATCH v2 6/8] target/riscv: Implement Smdbltrp sret, mret and mnret behavior
` [PATCH v2 7/8] target/riscv: Implement Smdbltrp behavior
` [PATCH v2 8/8] target/riscv: Add Smdbltrp ISA extension enable switch
[PATCH v2 1/1] target/riscv: enable floating point unit
2024-09-25 11:06 UTC (2+ messages)
[PATCH 0/2] target/riscv/kvm: Update kvm exts to Linux v6.11
2024-09-24 13:24 UTC (7+ messages)
` [PATCH 1/2] linux-headers: Update "
` [PATCH 2/2] target/riscv/kvm: Update kvm exts "
[PATCH 0/4] target/riscv/kvm: add riscv-aia bool props
2024-09-24 12:44 UTC (5+ messages)
` [PATCH 1/4] target/riscv/kvm: set 'aia_mode' to default in error path
` [PATCH 2/4] target/riscv/kvm: clarify how 'riscv-aia' default works
` [PATCH 3/4] target/riscv/kvm: add kvm-aia bools props
` [PATCH 4/4] target/riscv/kvm: deprecate riscv-aia string prop
[PATCH v3 00/34] Use g_assert_not_reached instead of (g_)assert(0, false)
2024-09-24 11:52 UTC (36+ messages)
` [PATCH v3 01/34] hw/acpi: replace assert(0) with g_assert_not_reached()
` [PATCH v3 02/34] hw/arm: "
` [PATCH v3 03/34] hw/net: "
` [PATCH v3 04/34] migration: "
` [PATCH v3 05/34] qobject: "
` [PATCH v3 06/34] target/ppc: "
` [PATCH v3 07/34] block: replace assert(false) "
` [PATCH v3 08/34] hw/hyperv: "
` [PATCH v3 09/34] hw/net: "
` [PATCH v3 10/34] hw/nvme: "
` [PATCH v3 11/34] hw/pci: "
` [PATCH v3 12/34] hw/ppc: "
` [PATCH v3 13/34] migration: "
` [PATCH v3 14/34] target/i386/kvm: "
` [PATCH v3 15/34] accel/tcg: remove break after g_assert_not_reached()
` [PATCH v3 16/34] block: "
` [PATCH v3 17/34] hw/acpi: "
` [PATCH v3 18/34] hw/net: "
` [PATCH v3 19/34] hw/scsi: "
` [PATCH v3 20/34] hw/tpm: "
` [PATCH v3 21/34] target/arm: "
` [PATCH v3 22/34] target/riscv: "
` [PATCH v3 23/34] fpu: "
` [PATCH v3 24/34] tcg/loongarch64: "
` [PATCH v3 25/34] include/qemu: remove return "
` [PATCH v3 26/34] hw/hyperv: "
` [PATCH v3 27/34] hw/net: "
` [PATCH v3 28/34] hw/pci: "
` [PATCH v3 29/34] hw/ppc: "
` [PATCH v3 30/34] migration: "
` [PATCH v3 31/34] qobject: "
` [PATCH v3 32/34] qom: "
` [PATCH v3 33/34] tests/qtest: "
` [PATCH v3 34/34] scripts/checkpatch.pl: emit error when using assert(false)
[PATCH v7 00/17] bsd-user: Comprehensive RISCV Support
2024-09-24 1:42 UTC (20+ messages)
` [PATCH v7 01/17] bsd-user: Implement RISC-V CPU initialization and main loop
` [PATCH v7 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling
` [PATCH v7 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions
` [PATCH v7 04/17] bsd-user: Implement RISC-V TLS register setup
` [PATCH v7 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection
` [PATCH v7 06/17] bsd-user: Define RISC-V register structures and register copying
` [PATCH v7 07/17] bsd-user: Add RISC-V signal trampoline setup function
` [PATCH v7 08/17] bsd-user: Implement RISC-V sysarch system call emulation
` [PATCH v7 09/17] bsd-user: Add RISC-V thread setup and initialization support
` [PATCH v7 10/17] bsd-user: Define RISC-V VM parameters and helper functions
` [PATCH v7 11/17] bsd-user: Define RISC-V system call structures and constants
` [PATCH v7 12/17] bsd-user: Add generic RISC-V64 target definitions
` [PATCH v7 13/17] bsd-user: Define RISC-V signal handling structures and constants
` [PATCH v7 14/17] bsd-user: Implement RISC-V signal trampoline setup functions
` [PATCH v7 15/17] bsd-user: Implement 'get_mcontext' for RISC-V
` [PATCH v7 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV
` [PATCH v7 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
[PATCH v4 00/12] tcg/riscv: Add support for vector
2024-09-23 10:10 UTC (22+ messages)
` [PATCH v4 01/12] util: Add RISC-V vector extension probe in cpuinfo
` [PATCH v4 02/12] tcg/riscv: Add basic support for vector
` [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops
[PATCH 0/6] linux-user: move all remaining archs to syscalltbl
2024-09-22 11:54 UTC (8+ messages)
` [PATCH 1/6] linux-user,aarch64: move to syscalltbl file
` [PATCH 2/6] linux-user,openrisc: "
` [PATCH 3/6] linux-user,riscv: "
` [PATCH 4/6] linux-user,hexagon: "
` [PATCH 5/6] linux-user,loongarch: "
` [PATCH 6/6] linux-user: update syscall.tbl to Linux v6.11
[PATCH 00/10] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions
2024-09-21 12:21 UTC (5+ messages)
` [PATCH 01/10] target/riscv: Add `ext_ssdbltrp` in RISCVCPUConfig
` [PATCH 06/10] target/riscv: Add `ext_smdbltrp` "
[PATCH v3 0/1] Add support for generating OpenSBI domains in the device tree
2024-09-19 21:16 UTC (4+ messages)
[PATCH v2 00/48] Use g_assert_not_reached instead of (g_)assert(0, false)
2024-09-19 2:01 UTC (4+ messages)
[PATCH v6 0/7] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions
2024-09-18 17:14 UTC (8+ messages)
` [PATCH v6 1/7] target/riscv: Set vdata.vm field for vector load/store whole register instructions
` [PATCH v6 2/7] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us
` [PATCH v6 3/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store
` [PATCH v6 4/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store
` [PATCH v6 5/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride load-only-first load instructions
` [PATCH v6 6/7] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
` [PATCH v6 7/7] target/riscv: Inline unit-stride ld/st and corresponding functions for performance
[PATCH 1/1] target/riscv: enable floating point unit
2024-09-18 16:27 UTC (14+ messages)
[PATCH 0/2] riscv: hw/intc: Fixes for standard conformance
2024-09-18 14:02 UTC (3+ messages)
` [PATCH 1/2] hw/intc: Make zeroth priority register read-only
` [PATCH 2/2] hw/intc: Don't clear pending bits on IRQ lowering
[PATCH v8] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI
2024-09-18 13:41 UTC (6+ messages)
` [PATCH v9] "
[PATCH v6 00/17] bsd-user: Comprehensive RISCV Support
2024-09-16 11:45 UTC
[PATCH v14 00/20] riscv support for control flow integrity extensions
2024-09-12 23:53 UTC (17+ messages)
` [PATCH v14 02/20] target/riscv: Add zicfilp extension
` [PATCH v14 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp
` [PATCH v14 04/20] target/riscv: save and restore elp state on priv transitions
` [PATCH v14 05/20] target/riscv: additional code information for sw check
` [PATCH v14 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp
` [PATCH v14 07/20] target/riscv: zicfilp `lpad` impl and branch tracking
` [PATCH v14 08/20] disas/riscv: enable `lpad` disassembly
` [PATCH v14 09/20] target/riscv: Expose zicfilp extension as a cpu property
` [PATCH v14 10/20] target/riscv: Add zicfiss extension
` [PATCH v14 11/20] target/riscv: introduce ssp and enabling controls for zicfiss
` [PATCH v14 13/20] target/riscv: mmu changes for zicfiss shadow stack protection
` [PATCH v14 16/20] target/riscv: implement zicfiss instructions
` [PATCH v14 17/20] target/riscv: compressed encodings for sspush and sspopchk
` [PATCH v14 18/20] disas/riscv: enable disassembly for zicfiss instructions
` [PATCH v14 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk
` [PATCH v14 20/20] target/riscv: Expose zicfiss extension as a cpu property
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