messages from 2025-10-15 12:00:36 to 2025-10-27 11:08:01 UTC [more...]
[PATCH 00/35] maintainer updates for 8.2 softfeeeze (ci, plugins, semihosting) pre-PR
2025-10-27 11:03 UTC (11+ messages)
` [PATCH 03/35] scripts/ci: move build-environment.yaml up a level
` [PATCH 06/35] scripts/ci: modify gitlab runner deb setup
` [PATCH 08/35] plugins: add API for registering discontinuity callbacks
` [PATCH 11/35] target/alpha: call plugin trap callbacks
` [PATCH 12/35] target/arm: "
` [PATCH 13/35] target/avr: "
` [PATCH 17/35] target/m68k: "
` [PATCH 28/35] target/xtensa: "
` [PATCH 29/35] tests: add plugin asserting correctness of discon event's to_pc
` [PATCH 31/35] tests: add test with interrupted memory accesses on rv64
[PATCH v2 0/5] RISC-V: NEORV32 CPU, devices, and machine
2025-10-27 10:09 UTC (6+ messages)
` [PATCH v2 1/5] target/riscv: add NEORV32 RV32 CPU type and vendor CSR hooks
` [PATCH v2 2/5] hw/misc: add NEORV32 SYSINFO block (CLK/MISC/SOC/CACHE)
` [PATCH v2 3/5] hw/char: add NEORV32 UART (CTRL/DATA, fifo, chardev)
` [PATCH v2 4/5] hw/ssi: add NEORV32 SPI controller (SSI master, CS command)
` [PATCH v2 5/5] hw/riscv: introduce 'neorv32' board, docs, and riscv32 device config
[PATCH] hw/riscv/riscv-iommu: Fix MemoryRegion owner
2025-10-27 9:39 UTC (2+ messages)
[PATCH 00/27] hw/sysbus: Spring cleanups (part 1)
2025-10-27 7:26 UTC (35+ messages)
` [PATCH 01/27] hw/qdev: Have qdev_get_gpio_out_connector() take const DeviceState arg
` [PATCH 02/27] hw/sysbus: Have various helpers take a const SysBusDevice argument
` [PATCH 03/27] hw/sysbus: Use memory_region_name()
` [PATCH 04/27] hw/i386/microvm: Use proper SysBus accessors
` [PATCH 05/27] hw/timer/hpet: "
` [PATCH 06/27] hw/acpi/cxl: "
` [PATCH 07/27] hw/sysbus: Add sysbus_has_pio() and sysbus_pio_get_address()
` [PATCH 08/27] hw/pci-bridge/pci_expander_bridge: Use proper SysBus accessors
` [PATCH 09/27] hw/platform-bus: Include missing 'system/memory.h' header
` [PATCH 10/27] hw/block/pflash: "
` [PATCH 11/27] hw/misc/unimp: "
` [PATCH 12/27] hw/misc/empty_slot: "
` [PATCH 13/27] hw/uefi: "
` [PATCH 14/27] hw/usb/imx: "
` [PATCH 15/27] hw/pci/pcihost: "
` [PATCH 16/27] hw/scsi/esp: "
` [PATCH 17/27] hw/avr: "
` [PATCH 18/27] hw/input/lassi: "
` [PATCH 19/27] hw/tricore: "
` [PATCH 20/27] hw/int/loongarch: "
` [PATCH 21/27] hw/rtc/m48t59: "
` [PATCH 22/27] hw/rtc/sun: Include 'exec/cpu-common.h' and 'system/memory.h' headers
` [PATCH 23/27] hw/xilinx: "
` [PATCH 24/27] hw/mips: Include missing 'system/memory.h' header
` [PATCH 25/27] hw/sparc: "
` [PATCH 26/27] hw/riscv: "
` [PATCH 27/27] hw/rx: "
[PATCH] target/riscv/riscv-qmp-cmds.c: coverity-related fixes
2025-10-23 15:36 UTC (4+ messages)
[PATCH] target/riscv/insn_trans: Fix sc.w & sc.d incorrect behavior on misaligned access
2025-10-23 12:20 UTC
[PATCH] remove redundant typedef when use OBJECT_DECLARE_SIMPLE_TYPE
2025-10-23 6:55 UTC (2+ messages)
[PATCH] accel/tcg: Pass actual memop_size to tlb_fill instead of 0
2025-10-23 6:38 UTC (6+ messages)
[PATCH v2] char: rename CharBackend->CharFrontend
2025-10-23 4:52 UTC (4+ messages)
[PATCH v3 0/2] Make PMP granularity configurable
2025-10-23 2:37 UTC (6+ messages)
` [PATCH v3 1/2] target/riscv: "
` [PATCH v3 2/2] target/riscv: Make PMP CSRs conform to WARL constraints
[PATCH v2] target/riscv: Fix a uninitialized variable warning
2025-10-23 0:04 UTC (3+ messages)
[PATCH] target/riscv: fix riscv_cpu_sirq_pending() mask
2025-10-22 23:58 UTC (3+ messages)
[PATCH v2] target/riscv/riscv-qmp-cmds.c: coverity-related fixes
2025-10-22 23:58 UTC (3+ messages)
[PATCH] target/riscv/kvm: fix env->priv setting in reset_regs_csr()
2025-10-22 23:57 UTC (3+ messages)
[PATCH v2 9/9] hw/char: Simplify when qemu_chr_fe_write() could not write
2025-10-22 15:07 UTC
[PATCH 7/7] hw/char: Simplify when qemu_chr_fe_write() could not write
2025-10-22 14:49 UTC
[PATCH v9 0/2] target/riscv：Fix riscv64 kvm migration
2025-10-22 11:47 UTC (3+ messages)
` [PATCH v9 1/2] Set KVM initial privilege mode and mp_state
[PATCH v11 0/8] Support RISC-V IOPMP
2025-10-22 6:52 UTC (6+ messages)
` [PATCH v11 6/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
[PATCH v1 0/2] Make PMP granularity configurable
2025-10-22 2:35 UTC (7+ messages)
` [PATCH v1 1/2] target/riscv: "
` [PATCH v1 2/2] target/riscv: Make PMP CSRs conform to WARL constraints
` [PATCH v2 0/2] Make PMP granularity configurable
` [PATCH v2 1/2] target/riscv: "
` [PATCH v2 2/2] target/riscv: Make PMP CSRs conform to WARL constraints
[PATCH v3 00/18] Implements RISC-V WorldGuard extension v0.4
2025-10-21 16:21 UTC (19+ messages)
` [PATCH v3 01/18] accel/tcg: Store section pointer in CPUTLBEntryFull
` [PATCH v3 02/18] system/physmem: Remove the assertion of page-aligned section number
` [PATCH v3 03/18] accel/tcg: memory access from CPU will pass access_type to IOMMU
` [PATCH v3 04/18] exec: Add RISC-V WorldGuard WID to MemTxAttrs
` [PATCH v3 05/18] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config
` [PATCH v3 06/18] target/riscv: Add CPU options of WorldGuard CPU extension
` [PATCH v3 07/18] target/riscv: Add hard-coded CPU state of WG extension
` [PATCH v3 08/18] target/riscv: Add defines for WorldGuard CSRs
` [PATCH v3 09/18] target/riscv: Allow global WG config to set WG CPU callbacks
` [PATCH v3 10/18] target/riscv: Implement WorldGuard CSRs
` [PATCH v3 11/18] target/riscv: Add WID to MemTxAttrs of CPU memory transactions
` [PATCH v3 12/18] target/riscv: Expose CPU options of WorldGuard
` [PATCH v3 13/18] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU
` [PATCH v3 14/18] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker
` [PATCH v3 15/18] hw/misc: riscv_wgchecker: Implement wgchecker slot registers
` [PATCH v3 16/18] hw/misc: riscv_wgchecker: Implement correct block-access behavior
` [PATCH v3 17/18] hw/misc: riscv_wgchecker: Check the slot settings in translate
` [PATCH v3 18/18] hw/riscv: virt: Add WorldGuard support
[PATCH] char: rename CharBackend->CharFrontend
2025-10-21 15:33 UTC (9+ messages)
[PATCH v1 0/1] hw/riscv: adding support for NeoRV32 RiscV MCU
2025-10-21 5:00 UTC (4+ messages)
` [PATCH v1 1/1] "
[PATCH v13 00/13] riscv: Add support for MIPS P8700 CPU
2025-10-21 0:28 UTC (15+ messages)
` [PATCH v13 02/13] target/riscv: Add cpu_set_exception_base
` [PATCH v13 03/13] target/riscv: Add MIPS P8700 CPU
` [PATCH v13 01/13] hw/intc: Allow gaps in hartids for aclint and aplic
` [PATCH v13 06/13] target/riscv: Add mips.pref instruction
` [PATCH v13 04/13] target/riscv: Add MIPS P8700 CSRs
` [PATCH v13 05/13] target/riscv: Add mips.ccmov instruction
` [PATCH v13 07/13] target/riscv: Add Xmipslsp instructions
` [PATCH v13 08/13] hw/misc: Add RISC-V CMGCR device implementation
` [PATCH v13 11/13] hw/riscv: Add support for MIPS Boston-aia board mode
` [PATCH v13 09/13] hw/misc: Add RISC-V CPC device implementation
` [PATCH v13 10/13] hw/riscv: Add support for RISCV CPS
` [PATCH v13 12/13] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
` [PATCH v13 13/13] test/functional: Add test for boston-aia board
[PATCH] target/riscv: Fix a uninitialized variable warning
2025-10-20 9:27 UTC (4+ messages)
[PATCH v8 16/25] target/riscv: call plugin trap callbacks
2025-10-19 15:18 UTC (3+ messages)
` [PATCH v8 24/25] tests: add test for double-traps on rv64
` [PATCH v8 25/25] tests: add test with interrupted memory accesses "
[PATCH v12 00/13] riscv: Add support for MIPS P8700 CPU
2025-10-18 15:43 UTC (16+ messages)
` [PATCH v12 02/13] target/riscv: Add cpu_set_exception_base
` [PATCH v12 01/13] hw/intc: Allow gaps in hartids for aclint and aplic
` [PATCH v12 03/13] target/riscv: Add MIPS P8700 CPU
` [PATCH v12 04/13] target/riscv: Add MIPS P8700 CSRs
` [PATCH v12 06/13] target/riscv: Add mips.pref instruction
` [PATCH v12 05/13] target/riscv: Add mips.ccmov instruction
` [PATCH v12 07/13] target/riscv: Add Xmipslsp instructions
` [PATCH v12 09/13] hw/misc: Add RISC-V CPC device implementation
` [PATCH v12 08/13] hw/misc: Add RISC-V CMGCR "
` [PATCH v12 11/13] hw/riscv: Add support for MIPS Boston-aia board mode
` [PATCH v12 12/13] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
` [PATCH v12 10/13] hw/riscv: Add support for RISCV CPS
` [PATCH v12 13/13] test/functional: Add test for boston-aia board
[PATCH 00/22] hw/core/cpu: Remove @CPUState::as field
2025-10-18 5:52 UTC (3+ messages)
` [PATCH 06/22] hw/m86k: Get cpu first addr space with cpu_get_address_space()
[PATCH 00/17] hw/riscv, target/riscv: initial e-trace support
2025-10-17 17:35 UTC (4+ messages)
` [PATCH 14/17] hw/riscv, target/riscv: send resync updiscon trace packets
[PATCH 00/13] target/riscv: Centralize MO_TE uses in a pair of helpers
2025-10-17 12:50 UTC (4+ messages)
` [PATCH 12/13] target/riscv: Introduce mo_endian() helper
[PATCH v1 0/2] Make PMP granularity configurable
2025-10-17 12:29 UTC (6+ messages)
` [PATCH v1 1/2] target/riscv: "
` [PATCH v1 2/2] target/riscv: Make PMP CSRs conform to WARL constraints
[PATCH v2] docs/system/security: Restrict "virtualization use case" to specific machines
2025-10-17 11:42 UTC (6+ messages)
[PATCH v3] aplic: fix mask for smsiaddrcfgh
2025-10-17 2:59 UTC (3+ messages)
[PATCH 0/6] target: Remove remnant legacy cpu_physical_memory_*() calls
2025-10-16 15:08 UTC (2+ messages)
[PATCH 00/16] overall: Replace HOST_BIG_ENDIAN #ifdef with runtime if() check
2025-10-16 12:07 UTC (4+ messages)
[PATCH v2 00/18] Implements RISC-V WorldGuard extension v0.4
2025-10-16 3:33 UTC (6+ messages)
` [PATCH v2 04/18] exec: Add RISC-V WorldGuard WID to MemTxAttrs
[PATCH v11 00/13] riscv: Add support for MIPS P8700 CPU
2025-10-15 13:04 UTC (12+ messages)
` [PATCH v11 06/13] target/riscv: Add mips.pref instruction
` [PATCH v11 04/13] target/riscv: Add MIPS P8700 CSRs
` [PATCH v11 05/13] target/riscv: Add mips.ccmov instruction
` [PATCH v11 08/13] hw/misc: Add RISC-V CMGCR device implementation
` [PATCH v11 07/13] target/riscv: Add Xmipslsp instructions
` [PATCH v11 11/13] hw/riscv: Add support for MIPS Boston-aia board mode
` [PATCH v11 09/13] hw/misc: Add RISC-V CPC device implementation
` [PATCH v11 12/13] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
` [PATCH v11 13/13] test/functional: Add test for boston-aia board
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