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Mon, 17 Jan 2022 19:35:33 -0800 (PST) MIME-Version: 1.0 References: <20220118011711.7243-1-liweiwei@iscas.ac.cn> <20220118011711.7243-6-liweiwei@iscas.ac.cn> In-Reply-To: <20220118011711.7243-6-liweiwei@iscas.ac.cn> From: Anup Patel Date: Tue, 18 Jan 2022 09:05:21 +0530 Message-ID: Subject: Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension To: Weiwei Li Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , "open list:RISC-V" , QEMU Developers , wangjunqiang@iscas.ac.cn, =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= , Heiko Stuebner Content-Type: text/plain; charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: none client-ip=2a00:1450:4864:20::32e; envelope-from=anup@brainfault.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Jan 2022 03:35:41 -0000 On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: > > - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently > - add PTE_PBMT bit check for inner PTE > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Cc: Heiko Stuebner > Cc: Anup Patel > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/cpu_bits.h | 2 ++ > target/riscv/cpu_helper.c | 4 +++- > 4 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 45ac98e06b..4f82bd00a3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > > DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c3d1845ca1..53f314c752 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -329,6 +329,7 @@ struct RISCVCPU { > bool ext_icsr; > bool ext_svinval; > bool ext_svnapot; > + bool ext_svpbmt; > bool ext_zfh; > bool ext_zfhmin; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 5501e9698b..24b7eb2b1f 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -486,7 +486,9 @@ typedef enum { > #define PTE_A 0x040 /* Accessed */ > #define PTE_D 0x080 /* Dirty */ > #define PTE_SOFT 0x300 /* Reserved for Software */ > +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ > #define PTE_N 0x8000000000000000 /* NAPOT translation */ > +#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ > > /* Page table PPN shift amount */ > #define PTE_PPN_SHIFT 10 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index c276760c7f..9fffaccffb 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -625,9 +625,11 @@ restart: > if (!(pte & PTE_V)) { > /* Invalid PTE */ > return TRANSLATE_FAIL; > + } else if (!cpu->cfg.ext_svpbmt && (pte & (target_ulong)PTE_PBMT)) { Rather than, type-casting defines here you can simply define ULL constants. E.g. #define PTE_PBMT 0x6000000000000000ULL > + return TRANSLATE_FAIL; > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > /* Inner PTE, continue walking */ > - if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) { > + if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_ATTR)) { > return TRANSLATE_FAIL; > } > base = ppn << PGSHIFT; > -- > 2.17.1 > Regards, Anup