From: Robert Foley <robert.foley@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-devel@nongnu.org, cota@braap.org,
aaron@os.amperecomputing.com,
Peter Puhov <peter.puhov@linaro.org>,
kuhn.chenqun@huawei.com, robhenry@microsoft.com, fam@euphon.net,
berrange@redhat.com, f4bug@amsat.org,
Richard Henderson <richard.henderson@linaro.org>,
balrogg@gmail.com, aurelien@aurel32.net, pbonzini@redhat.com,
stefanha@redhat.com, stefanb@linux.vnet.ibm.com,
marcandre.lureau@redhat.com, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v2 14/19] target/riscv: progressively load the instruction during decode
Date: Fri, 14 Feb 2020 14:34:49 -0500 [thread overview]
Message-ID: <CAEyhzFs2Ge7zb1CfByWBfatgB+mbwndMwKFFsEZ=vbALMUmxYA@mail.gmail.com> (raw)
In-Reply-To: <20200213225109.13120-15-alex.bennee@linaro.org>
On Thu, 13 Feb 2020 at 18:00, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> The plugin system would throw up a harmless warning when it detected
> that a disassembly of an instruction didn't use all it's bytes. Fix
> the riscv decoder to only load the instruction bytes it needs as it
> needs them.
>
> This drops opcode from the ctx in favour if passing the appropriately
> sized opcode down a few levels of the decode.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Robert Foley <robert.foley@linaro.org>
prev parent reply other threads:[~2020-02-14 19:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200213225109.13120-1-alex.bennee@linaro.org>
2020-02-13 22:51 ` [PATCH v2 14/19] target/riscv: progressively load the instruction during decode Alex Bennée
2020-02-14 1:23 ` Alistair Francis
2020-02-14 19:34 ` Robert Foley [this message]
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