From: Alexandre Ghiti <alexghiti@rivosinc.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: Andrew Jones <ajones@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Frank Chang <frank.chang@sifive.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Ludovic Henry <ludovic@rivosinc.com>
Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode
Date: Thu, 19 Jan 2023 14:00:27 +0100 [thread overview]
Message-ID: <CAHVXubiW2OaMhe3STLLMz=wDPJeY8hvPHbuBJgL7KZyw4=pRpw@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKNcd3JOZgPb23idrzVjxHj+HHwPz6f6xPEp2oVGJEZKpg@mail.gmail.com>
Hi Alistair, Andrew,
On Thu, Jan 19, 2023 at 1:25 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Jan 18, 2023 at 10:19 PM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
> > On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote:
> > > On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones <ajones@ventanamicro.com> wrote:
> > > >
> > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
> > ...
> > > > > +
> > > > > + /* Get rid of 32-bit/64-bit incompatibility */
> > > > > + for (int i = 0; i < 16; ++i) {
> > > > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) {
> > > >
> > > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly
> > > > accepted as an alias. I think we should simply not define the sv32
> > > > property for rv64 nor the rv64-only modes for rv32. So, down in
> > > > riscv_add_satp_mode_properties() we can add some
> > > >
> > > > #if defined(TARGET_RISCV32)
> > > > ...
> > > > #elif defined(TARGET_RISCV64)
> > > > ...
> > > > #endif
> > >
> > > Do not add any #if defined(TARGET_RISCV32) to QEMU.
> > >
> > > We are aiming for the riscv64-softmmu to be able to emulate 32-bit
> > > CPUs and compile time macros are the wrong solution here. Instead you
> > > can get the xlen of the hart and use that.
> > >
> >
> > Does this mean we want to be able to do the following?
> >
> > qemu-system-riscv64 -cpu rv32,sv32=on ...
>
> That's the plan
>
> >
> > If so, then can we move the object_property_add() for sv32 to
> > rv32_base_cpu_init() and the rest to rv64_base_cpu_init()?
> > Currently, that would be doing the same thing as proposed above,
> > since those functions are under TARGET_RISCV* defines, but I guess
> > the object_property_add()'s would then be in more or less the right
> > places for when the 32-bit emulation support work is started.
>
> Sounds like a good idea :)
What about riscv_any_cpu_init and riscv_host_cpu_init?
>
> Alistair
>
> >
> > Thanks,
> > drew
next prev parent reply other threads:[~2023-01-19 13:00 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-13 10:34 [PATCH v5 0/2] riscv: Allow user to set the satp mode Alexandre Ghiti
2023-01-13 10:34 ` [PATCH v5 1/2] riscv: Pass Object to register_cpu_props instead of DeviceState Alexandre Ghiti
2023-01-16 4:06 ` Alistair Francis
2023-01-16 14:16 ` Frank Chang
2023-01-17 14:21 ` Andrew Jones
2023-01-13 10:34 ` [PATCH v5 2/2] riscv: Allow user to set the satp mode Alexandre Ghiti
2023-01-17 16:31 ` Andrew Jones
2023-01-18 0:28 ` Alistair Francis
2023-01-18 12:19 ` Andrew Jones
2023-01-19 0:25 ` Alistair Francis
2023-01-19 13:00 ` Alexandre Ghiti [this message]
2023-01-19 14:49 ` Andrew Jones
2023-01-19 23:46 ` Alistair Francis
2023-01-20 9:53 ` Andrew Jones
2023-01-20 12:44 ` Alexandre Ghiti
2023-01-20 13:25 ` Andrew Jones
2023-01-18 16:29 ` Alexandre Ghiti
2023-01-18 17:41 ` Andrew Jones
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