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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id c184sm36953pfa.39.2020.02.12.11.28.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Feb 2020 11:28:30 -0800 (PST) Subject: Re: [PATCH v4 4/4] target/riscv: add vector configure instruction To: LIU Zhiwei , alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Cc: wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20200210081240.11481-1-zhiwei_liu@c-sky.com> <20200210081240.11481-5-zhiwei_liu@c-sky.com> <053777e2-7180-5584-cf7f-7876800d9dc8@linaro.org> From: Richard Henderson Message-ID: Date: Wed, 12 Feb 2020 11:28:28 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Feb 2020 19:28:36 -0000 On 2/12/20 12:09 AM, LIU Zhiwei wrote: > > > On 2020/2/12 0:56, Richard Henderson wrote: >> On 2/10/20 8:12 AM, LIU Zhiwei wrote: >>>   static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, >>> -                                        target_ulong *cs_base, uint32_t >>> *flags) >>> +                                        target_ulong *cs_base, uint32_t >>> *pflags) >>>   { >>> +    uint32_t flags = 0; >>> +    uint32_t vlmax; >>> +    uint8_t vl_eq_vlmax; >> bool. > OK. > > Is it clearer to use "bool" here? Or it's wrong to use "uint8_t "? It is clearer. Using uint8_t makes me wonder what else you were going to put in that variable, but the answer from the code below is nothing. >>> +    if (sew > cpu->cfg.elen) { /* only set vill bit. */ >>> +        env->vext.vtype = FIELD_DP64(0, VTYPE, VILL, 1); >>> +        env->vext.vl = 0; >>> +        env->vext.vstart = 0; >>> +        return 0; >>> +    } >> You're missing checks against EDIV, VILL and the RESERVED field == 0. > This implementation does not support "Zvediv" . So I did not check it. I'm not > sure if I should check(ediv==0). > > I missed check  "VILL" filed.  Fix up it next patch. > > I'm not quite sure if I should set VILL if  the RESERVED field != 0. The manual says # If the vtype setting is not supported by the implementation, # then the vill bit is set in vtype, the remaining bits in # vtype are set to zero, and the vl register is also set # to zero. So yes, you most certainly have to check ediv == 0. By extension, I believe the entire RESERVED field should be checked. Otherwise, we don't get the same forward compatible behaviour for the next vector extension beyond Zvediv. r~