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Fri, 07 Aug 2026 01:32:14 -0700 (PDT) Received: from sifive.com ([136.226.240.165]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3925fa4fc7fsm1619706a91.0.2026.08.07.01.32.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2026 01:32:14 -0700 (PDT) Date: Fri, 7 Aug 2026 16:32:10 +0800 From: Max Chou To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , Chao Liu , Frank Chang Subject: Re: [PATCH 2/5] target/riscv: Add SiFive custom int8 matmul extension implied rules Message-ID: References: <20260721122034.1567146-1-max.chou@sifive.com> <20260721122034.1567146-3-max.chou@sifive.com> <0a052a0c-ab06-410a-a163-4ca6e8b7211f@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <0a052a0c-ab06-410a-a163-4ca6e8b7211f@oss.qualcomm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=max.chou@sifive.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 2026-08-06 18:07, Daniel Henrique Barboza wrote: > > > On 7/21/2026 9:20 AM, Max Chou wrote: > > From: Frank Chang > > > > Add SiFive custom int8 matmul extension implied rules to enable the > > implied extensions of SiFive custom int8 matmul extension recursively. > > > > Signed-off-by: Frank Chang > > Signed-off-by: Max Chou > > --- > > target/riscv/cpu.c | 19 +++++++++++++++++++ > > 1 file changed, 19 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index e643d7c7af..70baa054f9 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -2811,6 +2811,24 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = { > > }, > > }; > > +static RISCVCPUImpliedExtsRule XSFVQMACCDOD_IMPLIED = { > > + .ext = CPU_CFG_OFFSET(ext_xsfvqmaccdod), > > + .implied_multi_exts = { > > + CPU_CFG_OFFSET(ext_zve32x), > > + > > + RISCV_IMPLIED_EXTS_RULE_END > > + }, > > +}; > > + > > +static RISCVCPUImpliedExtsRule XSFVQMACCQOQ_IMPLIED = { > > + .ext = CPU_CFG_OFFSET(ext_xsfvqmaccqoq), > > + .implied_multi_exts = { > > + CPU_CFG_OFFSET(ext_zve32x), > > + > > + RISCV_IMPLIED_EXTS_RULE_END > > + }, > > +}; > > + > > RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { > > &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, > > &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, > > @@ -2832,6 +2850,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { > > &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SHA_IMPLIED, > > &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, > > &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED, > > + &XSFVQMACCDOD_IMPLIED, &XSFVQMACCQOQ_IMPLIED, > > Not related to this patch but I wonder if we should put one rule per line > in this array. Every once in a while we have to add a rule that is > in a line that already has a lot of stuff, then we need to change multiple > lines to accommodate the new rule. > > Hi Daniel, Actually, I share the same observation and thought, and I agree with you. Let me update this part in v2. Thanks for the suggestion! rnax > As for the patch: > > > > Reviewed-by: Daniel Henrique Barboza > > > > > > > NULL > > }; >