Re: [PATCH 08/10] target/riscv: bypass smstateen check in debugger mode

[Chao Liu via <qemu-riscv@nongnu.org>]

On Wed, Sep 30, 2026 at 03:24:34PM +0800, Daniel Henrique Barboza wrote:
> 
> 
> On 9/11/2026 9:27 AM, Marc-André Lureau wrote:
> > Allow to read CSRs gated by Smstateen extension when env->debugger.
> > 
> > Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> > ---
> >   target/riscv/tcg/csr.c | 3 ++-
> >   1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> > index bd4b6dc114bc..93a7f419f29f 100644
> > --- a/target/riscv/tcg/csr.c
> > +++ b/target/riscv/tcg/csr.c
> > @@ -53,7 +53,8 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
> >   {
> >       bool virt = env->virt_enabled;
> > -    if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
> > +    if (env->debugger || env->priv == PRV_M ||
> > +        !riscv_cpu_cfg(env)->ext_smstateen) {
> 
> We have an going work in qemu-riscv (sdext, currently on v10) that adds
> a new 'debug' mode that is higher than the machine mode (PRV_M).  It
> already uses env->debugger in its logic.
> 
Looks good to me. Debug Mode uses M-mode privileges as a baseline, with
additional access to debug-only CSRs.

One thought came to mind here that I'd like to share: for CSR access,
`env->debugger` and 'debug' mode both indicate a debugging context,
entered through QEMU's GDB stub or the CPU's architectural debug
mechanism. CSR access rules differ in that context.

I think a shared helper could check these two flags together,
and include `PRV_M` where the same access rules apply. This is outside
the scope of this patch, but we can look into it once Sdext is merged.
I'll work on it if I have time.


Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> I believe this change is already in line with what we want there, i.e. debug
> mode having at least the same accesses as PRV_M.
> 
> 
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> 
> 
> 
> >           return RISCV_EXCP_NONE;
> >       }
> > 
>