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[95.125.227.10]) by smtp.gmail.com with ESMTPSA id k8sm2583590wrn.91.2021.11.11.03.46.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Nov 2021 03:46:57 -0800 (PST) Subject: Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN To: LIU Zhiwei , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com References: <20211111055800.42672-1-zhiwei_liu@c-sky.com> <20211111055800.42672-20-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: Date: Thu, 11 Nov 2021 12:46:54 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211111055800.42672-20-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::332 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -52 X-Spam_score: -5.3 X-Spam_bar: ----- X-Spam_report: (-5.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.999, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Nov 2021 11:47:01 -0000 On 11/11/21 6:57 AM, LIU Zhiwei wrote: > @@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) > /* This instruction ignores LMUL and vector register groups */ > int maxsz = s->vlen >> 3; > TCGv_i64 t1; > + TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO); A reminder that this is zero-extend for v0.7.1 and sign-extend for v1.0.0. > @@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) > } > > t1 = tcg_temp_new_i64(); > - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); > + tcg_gen_extu_tl_i64(t1, src1); Likewise. > vec_element_storei(s, a->rd, 0, t1); > tcg_temp_free_i64(t1); > done: > @@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s, arg_rmrr *a) > (a->rd != a->rs2)); > } > > +/* OPIVXU without GVEC IR */ > +#define GEN_OPIVXU_TRANS(NAME, CHECK) \ > +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > +{ \ > + if (CHECK(s, a)) { \ > + static gen_helper_opivx * const fns[4] = { \ > + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ > + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ > + }; \ > + \ > + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ > + fns[s->sew], s, EXT_ZERO); \ > + } \ > + return false; \ > +} > + > GEN_OPIVX_TRANS(vslideup_vx, slideup_check) > -GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) > +GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check) > GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) > > GEN_OPIVX_TRANS(vslidedown_vx, opivx_check) > -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check) > +GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check) > GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check) Likewise. So if this patch set goes in after rvv 1.0, this whole patch may be dropped. r~