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Tue, 07 Sep 2021 23:27:13 -0700 (PDT) Received: from [192.168.127.34] ([185.81.138.20]) by smtp.gmail.com with ESMTPSA id ly7sm438432ejb.109.2021.09.07.23.27.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Sep 2021 23:27:12 -0700 (PDT) Subject: Re: [PATCH v2 1/3] target/riscv: Set the opcode in DisasContext To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com References: <2540484d3fb928600d403182529bf345b2b1f915.1631076834.git.alistair.francis@wdc.com> From: Richard Henderson Message-ID: Date: Wed, 8 Sep 2021 08:27:09 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <2540484d3fb928600d403182529bf345b2b1f915.1631076834.git.alistair.francis@wdc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.332, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Sep 2021 06:27:20 -0000 On 9/8/21 6:54 AM, Alistair Francis wrote: > From: Alistair Francis > > Signed-off-by: Alistair Francis > --- > target/riscv/translate.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index e356fc6c46..25670be435 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -485,20 +485,20 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > /* Include the auto-generated decoder for 16 bit insn */ > #include "decode-insn16.c.inc" > > -static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) > +static void decode_opc(CPURISCVState *env, DisasContext *ctx) > { > /* check for compressed insn */ > - if (extract16(opcode, 0, 2) != 3) { > + if (extract16(ctx->opcode, 0, 2) != 3) { > if (!has_ext(ctx, RVC)) { > gen_exception_illegal(ctx); > } else { > ctx->pc_succ_insn = ctx->base.pc_next + 2; > - if (!decode_insn16(ctx, opcode)) { > + if (!decode_insn16(ctx, ctx->opcode)) { > gen_exception_illegal(ctx); > } > } > } else { > - uint32_t opcode32 = opcode; > + uint32_t opcode32 = ctx->opcode; > opcode32 = deposit32(opcode32, 16, 16, > translator_lduw(env, ctx->base.pc_next + 2)); You needed to write back to ctx->opcode here. I think that all of the other changes are less than ideal -- let the value stay in a register as long as possible and drop them to memory immediately before calling decode_insn{16,32}, just before the write to pc_succ_insn in both cases. r~ > ctx->pc_succ_insn = ctx->base.pc_next + 4; > @@ -561,9 +561,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > { > DisasContext *ctx = container_of(dcbase, DisasContext, base); > CPURISCVState *env = cpu->env_ptr; > - uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); > + ctx->opcode = translator_lduw(env, ctx->base.pc_next); > > - decode_opc(env, ctx, opcode16); > + decode_opc(env, ctx); > ctx->base.pc_next = ctx->pc_succ_insn; > ctx->w = false; > >