* [PATCH 1/5] hw/timer/hpet: Reorganize register decoding
2025-05-20 15:27 [PATCH 0/5] hpet, rust: miscellaneous cleanup Zhao Liu
@ 2025-05-20 15:27 ` Zhao Liu
2025-05-20 15:27 ` [PATCH 2/5] hw/timer/hpet: Adjust num_timers in hpet_init() Zhao Liu
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Zhao Liu @ 2025-05-20 15:27 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, qemu-rust, Dapeng Mi, Zhao Liu
For Rust HPET, since the commit 519088b7cf6d ("rust: hpet: decode HPET
registers into enums"), it decodes register address by checking if the
register belongs to global register space. And for C HPET, it checks
timer register space first.
While both approaches are fine, it's best to be as consistent as
possible.
Synchronize changes from the rust side to C side.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Picked from <20250218073702.3299300-1-zhao1.liu@intel.com>. But because
of Rust code base change, it's enough to just sync the changes.
---
hw/timer/hpet.c | 166 ++++++++++++++++++++++++------------------------
1 file changed, 84 insertions(+), 82 deletions(-)
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index d1b7bc52b7be..0fd1337a1564 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -426,30 +426,11 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
uint64_t cur_tick;
trace_hpet_ram_read(addr);
+ addr &= ~4;
- /*address range of all TN regs*/
- if (addr >= 0x100 && addr <= 0x3ff) {
- uint8_t timer_id = (addr - 0x100) / 0x20;
- HPETTimer *timer = &s->timer[timer_id];
-
- if (timer_id > s->num_timers) {
- trace_hpet_timer_id_out_of_range(timer_id);
- return 0;
- }
-
- switch (addr & 0x18) {
- case HPET_TN_CFG: // including interrupt capabilities
- return timer->config >> shift;
- case HPET_TN_CMP: // comparator register
- return timer->cmp >> shift;
- case HPET_TN_ROUTE:
- return timer->fsb >> shift;
- default:
- trace_hpet_ram_read_invalid();
- break;
- }
- } else {
- switch (addr & ~4) {
+ /*address range of all global regs*/
+ if (addr <= 0xff) {
+ switch (addr) {
case HPET_ID: // including HPET_PERIOD
return s->capability >> shift;
case HPET_CFG:
@@ -468,6 +449,26 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
trace_hpet_ram_read_invalid();
break;
}
+ } else {
+ uint8_t timer_id = (addr - 0x100) / 0x20;
+ HPETTimer *timer = &s->timer[timer_id];
+
+ if (timer_id > s->num_timers) {
+ trace_hpet_timer_id_out_of_range(timer_id);
+ return 0;
+ }
+
+ switch (addr & 0x1f) {
+ case HPET_TN_CFG: // including interrupt capabilities
+ return timer->config >> shift;
+ case HPET_TN_CMP: // comparator register
+ return timer->cmp >> shift;
+ case HPET_TN_ROUTE:
+ return timer->fsb >> shift;
+ default:
+ trace_hpet_ram_read_invalid();
+ break;
+ }
}
return 0;
}
@@ -482,9 +483,67 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
uint64_t old_val, new_val, cleared;
trace_hpet_ram_write(addr, value);
+ addr &= ~4;
- /*address range of all TN regs*/
- if (addr >= 0x100 && addr <= 0x3ff) {
+ /*address range of all global regs*/
+ if (addr <= 0xff) {
+ switch (addr) {
+ case HPET_ID:
+ return;
+ case HPET_CFG:
+ old_val = s->config;
+ new_val = deposit64(old_val, shift, len, value);
+ new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
+ s->config = new_val;
+ if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
+ /* Enable main counter and interrupt generation. */
+ s->hpet_offset =
+ ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ for (i = 0; i < s->num_timers; i++) {
+ if (timer_enabled(&s->timer[i]) && (s->isr & (1 << i))) {
+ update_irq(&s->timer[i], 1);
+ }
+ hpet_set_timer(&s->timer[i]);
+ }
+ } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
+ /* Halt main counter and disable interrupt generation. */
+ s->hpet_counter = hpet_get_ticks(s);
+ for (i = 0; i < s->num_timers; i++) {
+ hpet_del_timer(&s->timer[i]);
+ }
+ }
+ /* i8254 and RTC output pins are disabled
+ * when HPET is in legacy mode */
+ if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
+ qemu_set_irq(s->pit_enabled, 0);
+ qemu_irq_lower(s->irqs[0]);
+ qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
+ } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
+ qemu_irq_lower(s->irqs[0]);
+ qemu_set_irq(s->pit_enabled, 1);
+ qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
+ }
+ break;
+ case HPET_STATUS:
+ new_val = value << shift;
+ cleared = new_val & s->isr;
+ for (i = 0; i < s->num_timers; i++) {
+ if (cleared & (1 << i)) {
+ update_irq(&s->timer[i], 0);
+ }
+ }
+ break;
+ case HPET_COUNTER:
+ if (hpet_enabled(s)) {
+ trace_hpet_ram_write_counter_write_while_enabled();
+ }
+ s->hpet_counter = deposit64(s->hpet_counter, shift, len, value);
+ break;
+ default:
+ trace_hpet_ram_write_invalid();
+ break;
+ }
+ } else {
uint8_t timer_id = (addr - 0x100) / 0x20;
HPETTimer *timer = &s->timer[timer_id];
@@ -550,63 +609,6 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
break;
}
return;
- } else {
- switch (addr & ~4) {
- case HPET_ID:
- return;
- case HPET_CFG:
- old_val = s->config;
- new_val = deposit64(old_val, shift, len, value);
- new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
- s->config = new_val;
- if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
- /* Enable main counter and interrupt generation. */
- s->hpet_offset =
- ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- for (i = 0; i < s->num_timers; i++) {
- if (timer_enabled(&s->timer[i]) && (s->isr & (1 << i))) {
- update_irq(&s->timer[i], 1);
- }
- hpet_set_timer(&s->timer[i]);
- }
- } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
- /* Halt main counter and disable interrupt generation. */
- s->hpet_counter = hpet_get_ticks(s);
- for (i = 0; i < s->num_timers; i++) {
- hpet_del_timer(&s->timer[i]);
- }
- }
- /* i8254 and RTC output pins are disabled
- * when HPET is in legacy mode */
- if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
- qemu_set_irq(s->pit_enabled, 0);
- qemu_irq_lower(s->irqs[0]);
- qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
- } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
- qemu_irq_lower(s->irqs[0]);
- qemu_set_irq(s->pit_enabled, 1);
- qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
- }
- break;
- case HPET_STATUS:
- new_val = value << shift;
- cleared = new_val & s->isr;
- for (i = 0; i < s->num_timers; i++) {
- if (cleared & (1 << i)) {
- update_irq(&s->timer[i], 0);
- }
- }
- break;
- case HPET_COUNTER:
- if (hpet_enabled(s)) {
- trace_hpet_ram_write_counter_write_while_enabled();
- }
- s->hpet_counter = deposit64(s->hpet_counter, shift, len, value);
- break;
- default:
- trace_hpet_ram_write_invalid();
- break;
- }
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/5] hw/timer/hpet: Adjust num_timers in hpet_init()
2025-05-20 15:27 [PATCH 0/5] hpet, rust: miscellaneous cleanup Zhao Liu
2025-05-20 15:27 ` [PATCH 1/5] hw/timer/hpet: Reorganize register decoding Zhao Liu
@ 2025-05-20 15:27 ` Zhao Liu
2025-05-20 15:16 ` Paolo Bonzini
2025-05-20 15:27 ` [PATCH 3/5] rust/hpet: Drop BalCell wrapper for num_timers Zhao Liu
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Zhao Liu @ 2025-05-20 15:27 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, qemu-rust, Dapeng Mi, Zhao Liu
Currently, HPET adjusts num_timers in hpet_realize(), and doesn't change
it in any other place. And this field is initialized as a property.
Therefore, it's possible to move such adjustments to hept_init(), so
that Rust side can synchronize this change.
Adjust num_timers in hpet_init().
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
hw/timer/hpet.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index 0fd1337a1564..48b1a9289f83 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -682,6 +682,12 @@ static void hpet_init(Object *obj)
/* HPET Area */
memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", HPET_LEN);
sysbus_init_mmio(sbd, &s->iomem);
+
+ if (s->num_timers < HPET_MIN_TIMERS) {
+ s->num_timers = HPET_MIN_TIMERS;
+ } else if (s->num_timers > HPET_MAX_TIMERS) {
+ s->num_timers = HPET_MAX_TIMERS;
+ }
}
static void hpet_realize(DeviceState *dev, Error **errp)
@@ -710,11 +716,6 @@ static void hpet_realize(DeviceState *dev, Error **errp)
sysbus_init_irq(sbd, &s->irqs[i]);
}
- if (s->num_timers < HPET_MIN_TIMERS) {
- s->num_timers = HPET_MIN_TIMERS;
- } else if (s->num_timers > HPET_MAX_TIMERS) {
- s->num_timers = HPET_MAX_TIMERS;
- }
for (i = 0; i < HPET_MAX_TIMERS; i++) {
timer = &s->timer[i];
timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer);
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/5] hw/timer/hpet: Adjust num_timers in hpet_init()
2025-05-20 15:27 ` [PATCH 2/5] hw/timer/hpet: Adjust num_timers in hpet_init() Zhao Liu
@ 2025-05-20 15:16 ` Paolo Bonzini
2025-05-21 7:34 ` Zhao Liu
0 siblings, 1 reply; 10+ messages in thread
From: Paolo Bonzini @ 2025-05-20 15:16 UTC (permalink / raw)
To: Zhao Liu; +Cc: qemu-devel, qemu-rust, Dapeng Mi
On 5/20/25 17:27, Zhao Liu wrote:
> Currently, HPET adjusts num_timers in hpet_realize(), and doesn't change
> it in any other place. And this field is initialized as a property.
Properties are initialized *after* hpet_init. For hw/timer/hpet you can
check s->num_timers and return an error if it's out of bounds, but for
the Rust version we don't have Error** support yet. :(
Queued 1-4-5 for now.
Paolo
> Therefore, it's possible to move such adjustments to hept_init(), so
> that Rust side can synchronize this change.
>
> Adjust num_timers in hpet_init().
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> hw/timer/hpet.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
> index 0fd1337a1564..48b1a9289f83 100644
> --- a/hw/timer/hpet.c
> +++ b/hw/timer/hpet.c
> @@ -682,6 +682,12 @@ static void hpet_init(Object *obj)
> /* HPET Area */
> memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", HPET_LEN);
> sysbus_init_mmio(sbd, &s->iomem);
> +
> + if (s->num_timers < HPET_MIN_TIMERS) {
> + s->num_timers = HPET_MIN_TIMERS;
> + } else if (s->num_timers > HPET_MAX_TIMERS) {
> + s->num_timers = HPET_MAX_TIMERS;
> + }
> }
>
> static void hpet_realize(DeviceState *dev, Error **errp)
> @@ -710,11 +716,6 @@ static void hpet_realize(DeviceState *dev, Error **errp)
> sysbus_init_irq(sbd, &s->irqs[i]);
> }
>
> - if (s->num_timers < HPET_MIN_TIMERS) {
> - s->num_timers = HPET_MIN_TIMERS;
> - } else if (s->num_timers > HPET_MAX_TIMERS) {
> - s->num_timers = HPET_MAX_TIMERS;
> - }
> for (i = 0; i < HPET_MAX_TIMERS; i++) {
> timer = &s->timer[i];
> timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer);
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 2/5] hw/timer/hpet: Adjust num_timers in hpet_init()
2025-05-20 15:16 ` Paolo Bonzini
@ 2025-05-21 7:34 ` Zhao Liu
0 siblings, 0 replies; 10+ messages in thread
From: Zhao Liu @ 2025-05-21 7:34 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Zhao Liu, qemu-devel, qemu-rust, Dapeng Mi
On Tue, May 20, 2025 at 05:16:22PM +0200, Paolo Bonzini wrote:
> Date: Tue, 20 May 2025 17:16:22 +0200
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: Re: [PATCH 2/5] hw/timer/hpet: Adjust num_timers in hpet_init()
>
> On 5/20/25 17:27, Zhao Liu wrote:
> > Currently, HPET adjusts num_timers in hpet_realize(), and doesn't change
> > it in any other place. And this field is initialized as a property.
>
> Properties are initialized *after* hpet_init. For hw/timer/hpet you can
> check s->num_timers and return an error if it's out of bounds, but for the
> Rust version we don't have Error** support yet. :(
Oops, yes.
(Note for myself,) the default property value is set before hpet_init(),
but the subsequent adjustments to property (via object_property_set_uint8())
need to take boundaries into account, which is why the num_timers adjustment
is placed in realize().
> Queued 1-4-5 for now.
Thanks!
Zhao
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/5] rust/hpet: Drop BalCell wrapper for num_timers
2025-05-20 15:27 [PATCH 0/5] hpet, rust: miscellaneous cleanup Zhao Liu
2025-05-20 15:27 ` [PATCH 1/5] hw/timer/hpet: Reorganize register decoding Zhao Liu
2025-05-20 15:27 ` [PATCH 2/5] hw/timer/hpet: Adjust num_timers in hpet_init() Zhao Liu
@ 2025-05-20 15:27 ` Zhao Liu
2025-05-20 15:27 ` [PATCH 4/5] rust: Fix Zhao's email address Zhao Liu
2025-05-20 15:27 ` [PATCH 5/5] rust: Fix the typos in doc Zhao Liu
4 siblings, 0 replies; 10+ messages in thread
From: Zhao Liu @ 2025-05-20 15:27 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, qemu-rust, Dapeng Mi, Zhao Liu
Currently, HPET adjusts num_timers in HPETState::realize(), and doesn't
change it in any other method. And this field is initialized as a
property.
Meanwhile, please note that as a property, someone may change its
default value in the future using qdev_prop_set_uint8() binding on
either the C side or Rust side after HPET object creation. However,
since this depends on QOM core code (on the C side) and all subsequent
processes occur on the C side, there's no need for additional safety
considerations as it doesn't cross FFI boundaries.
Therefore, this field could be immutable after init() so as not to be
necessary to have a BqlCell wrapper.
Adjust num_timers in HPETState::init() and drop the BqlCell wrapper.
Note, when num_timers came out of BqlCell, the capability field doesn't
need BqlCell as well since it's read-only. But from the view of
readability, it's best to keep consistent with the other registers.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
rust/hw/timer/hpet/src/hpet.rs | 37 +++++++++++++++-------------------
1 file changed, 16 insertions(+), 21 deletions(-)
diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src/hpet.rs
index 779681d65099..6cc6fa0aeda0 100644
--- a/rust/hw/timer/hpet/src/hpet.rs
+++ b/rust/hw/timer/hpet/src/hpet.rs
@@ -562,7 +562,7 @@ pub struct HPETState {
/// HPET timer array managed by this timer block.
#[doc(alias = "timer")]
timers: [BqlRefCell<HPETTimer>; HPET_MAX_TIMERS as usize],
- num_timers: BqlCell<u8>,
+ num_timers: u8,
num_timers_save: BqlCell<u8>,
/// Instance id (HPET timer block ID).
@@ -570,11 +570,6 @@ pub struct HPETState {
}
impl HPETState {
- // Get num_timers with `usize` type, which is useful to play with array index.
- fn get_num_timers(&self) -> usize {
- self.num_timers.get().into()
- }
-
const fn has_msi_flag(&self) -> bool {
self.flags & (1 << HPET_FLAG_MSI_SUPPORT_SHIFT) != 0
}
@@ -636,7 +631,7 @@ fn set_cfg_reg(&self, shift: u32, len: u32, val: u64) {
self.hpet_offset
.set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns());
- for timer in self.timers.iter().take(self.get_num_timers()) {
+ for timer in self.timers.iter().take(self.num_timers.into()) {
let mut t = timer.borrow_mut();
if t.is_int_enabled() && t.is_int_active() {
@@ -648,7 +643,7 @@ fn set_cfg_reg(&self, shift: u32, len: u32, val: u64) {
// Halt main counter and disable interrupt generation.
self.counter.set(self.get_ticks());
- for timer in self.timers.iter().take(self.get_num_timers()) {
+ for timer in self.timers.iter().take(self.num_timers.into()) {
timer.borrow_mut().del_timer();
}
}
@@ -671,7 +666,7 @@ fn set_int_status_reg(&self, shift: u32, _len: u32, val: u64) {
let new_val = val << shift;
let cleared = new_val & self.int_status.get();
- for (index, timer) in self.timers.iter().take(self.get_num_timers()).enumerate() {
+ for (index, timer) in self.timers.iter().take(self.num_timers.into()).enumerate() {
if cleared & (1 << index) != 0 {
timer.borrow_mut().update_irq(false);
}
@@ -715,6 +710,12 @@ unsafe fn init(&mut self) {
"hpet",
HPET_REG_SPACE_LEN,
);
+
+ if self.num_timers < HPET_MIN_TIMERS {
+ self.num_timers = HPET_MIN_TIMERS;
+ } else if self.num_timers > HPET_MAX_TIMERS {
+ self.num_timers = HPET_MAX_TIMERS;
+ }
}
fn post_init(&self) {
@@ -732,12 +733,6 @@ fn realize(&self) {
self.hpet_id.set(HPETFwConfig::assign_hpet_id());
- if self.num_timers.get() < HPET_MIN_TIMERS {
- self.num_timers.set(HPET_MIN_TIMERS);
- } else if self.num_timers.get() > HPET_MAX_TIMERS {
- self.num_timers.set(HPET_MAX_TIMERS);
- }
-
self.init_timer();
// 64-bit General Capabilities and ID Register; LegacyReplacementRoute.
self.capability.set(
@@ -745,7 +740,7 @@ fn realize(&self) {
1 << HPET_CAP_COUNT_SIZE_CAP_SHIFT |
1 << HPET_CAP_LEG_RT_CAP_SHIFT |
HPET_CAP_VENDER_ID_VALUE << HPET_CAP_VENDER_ID_SHIFT |
- ((self.get_num_timers() - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT | // indicate the last timer
+ ((self.num_timers - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT | // indicate the last timer
(HPET_CLK_PERIOD * FS_PER_NS) << HPET_CAP_CNT_CLK_PERIOD_SHIFT, // 10 ns
);
@@ -754,7 +749,7 @@ fn realize(&self) {
}
fn reset_hold(&self, _type: ResetType) {
- for timer in self.timers.iter().take(self.get_num_timers()) {
+ for timer in self.timers.iter().take(self.num_timers.into()) {
timer.borrow_mut().reset();
}
@@ -782,7 +777,7 @@ fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode {
GlobalRegister::try_from(addr).map(HPETRegister::Global)
} else {
let timer_id: usize = ((addr - 0x100) / 0x20) as usize;
- if timer_id <= self.get_num_timers() {
+ if timer_id <= self.num_timers.into() {
// TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id)
TimerRegister::try_from(addr & 0x18)
.map(|reg| HPETRegister::Timer(&self.timers[timer_id], reg))
@@ -853,12 +848,12 @@ fn pre_save(&self) -> i32 {
* also added to the migration stream. Check that it matches the value
* that was configured.
*/
- self.num_timers_save.set(self.num_timers.get());
+ self.num_timers_save.set(self.num_timers);
0
}
fn post_load(&self, _version_id: u8) -> i32 {
- for timer in self.timers.iter().take(self.get_num_timers()) {
+ for timer in self.timers.iter().take(self.num_timers.into()) {
let mut t = timer.borrow_mut();
t.cmp64 = t.calculate_cmp64(t.get_state().counter.get(), t.cmp);
@@ -883,7 +878,7 @@ fn is_offset_needed(&self) -> bool {
}
fn validate_num_timers(&self, _version_id: u8) -> bool {
- self.num_timers.get() == self.num_timers_save.get()
+ self.num_timers == self.num_timers_save.get()
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/5] rust: Fix Zhao's email address
2025-05-20 15:27 [PATCH 0/5] hpet, rust: miscellaneous cleanup Zhao Liu
` (2 preceding siblings ...)
2025-05-20 15:27 ` [PATCH 3/5] rust/hpet: Drop BalCell wrapper for num_timers Zhao Liu
@ 2025-05-20 15:27 ` Zhao Liu
2025-05-20 15:57 ` Peter Maydell
2025-05-20 15:27 ` [PATCH 5/5] rust: Fix the typos in doc Zhao Liu
4 siblings, 1 reply; 10+ messages in thread
From: Zhao Liu @ 2025-05-20 15:27 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, qemu-rust, Dapeng Mi, Zhao Liu
No one could find Zhao Liu via zhai1.liu@intel.com.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
rust/hw/timer/hpet/src/fw_cfg.rs | 2 +-
rust/hw/timer/hpet/src/hpet.rs | 2 +-
rust/hw/timer/hpet/src/lib.rs | 2 +-
rust/qemu-api/src/bitops.rs | 2 +-
rust/qemu-api/src/timer.rs | 2 +-
rust/qemu-api/tests/vmstate_tests.rs | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/rust/hw/timer/hpet/src/fw_cfg.rs b/rust/hw/timer/hpet/src/fw_cfg.rs
index aa08d2835194..6c10316104ce 100644
--- a/rust/hw/timer/hpet/src/fw_cfg.rs
+++ b/rust/hw/timer/hpet/src/fw_cfg.rs
@@ -1,5 +1,5 @@
// Copyright (C) 2024 Intel Corporation.
-// Author(s): Zhao Liu <zhai1.liu@intel.com>
+// Author(s): Zhao Liu <zhao1.liu@intel.com>
// SPDX-License-Identifier: GPL-2.0-or-later
use std::ptr::addr_of_mut;
diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src/hpet.rs
index 6cc6fa0aeda0..8f68372dee52 100644
--- a/rust/hw/timer/hpet/src/hpet.rs
+++ b/rust/hw/timer/hpet/src/hpet.rs
@@ -1,5 +1,5 @@
// Copyright (C) 2024 Intel Corporation.
-// Author(s): Zhao Liu <zhai1.liu@intel.com>
+// Author(s): Zhao Liu <zhao1.liu@intel.com>
// SPDX-License-Identifier: GPL-2.0-or-later
use std::{
diff --git a/rust/hw/timer/hpet/src/lib.rs b/rust/hw/timer/hpet/src/lib.rs
index 1954584a87e9..141aae229d4d 100644
--- a/rust/hw/timer/hpet/src/lib.rs
+++ b/rust/hw/timer/hpet/src/lib.rs
@@ -1,5 +1,5 @@
// Copyright (C) 2024 Intel Corporation.
-// Author(s): Zhao Liu <zhai1.liu@intel.com>
+// Author(s): Zhao Liu <zhao1.liu@intel.com>
// SPDX-License-Identifier: GPL-2.0-or-later
//! # HPET QEMU Device Model
diff --git a/rust/qemu-api/src/bitops.rs b/rust/qemu-api/src/bitops.rs
index 023ec1a99831..b1e3a530ab54 100644
--- a/rust/qemu-api/src/bitops.rs
+++ b/rust/qemu-api/src/bitops.rs
@@ -1,5 +1,5 @@
// Copyright (C) 2024 Intel Corporation.
-// Author(s): Zhao Liu <zhai1.liu@intel.com>
+// Author(s): Zhao Liu <zhao1.liu@intel.com>
// SPDX-License-Identifier: GPL-2.0-or-later
//! This module provides bit operation extensions to integer types.
diff --git a/rust/qemu-api/src/timer.rs b/rust/qemu-api/src/timer.rs
index 868bd88575f2..0a2d111d4909 100644
--- a/rust/qemu-api/src/timer.rs
+++ b/rust/qemu-api/src/timer.rs
@@ -1,5 +1,5 @@
// Copyright (C) 2024 Intel Corporation.
-// Author(s): Zhao Liu <zhai1.liu@intel.com>
+// Author(s): Zhao Liu <zhao1.liu@intel.com>
// SPDX-License-Identifier: GPL-2.0-or-later
use std::{
diff --git a/rust/qemu-api/tests/vmstate_tests.rs b/rust/qemu-api/tests/vmstate_tests.rs
index ad0fc5cd5dd0..bded836eb608 100644
--- a/rust/qemu-api/tests/vmstate_tests.rs
+++ b/rust/qemu-api/tests/vmstate_tests.rs
@@ -1,5 +1,5 @@
// Copyright (C) 2025 Intel Corporation.
-// Author(s): Zhao Liu <zhai1.liu@intel.com>
+// Author(s): Zhao Liu <zhao1.liu@intel.com>
// SPDX-License-Identifier: GPL-2.0-or-later
use std::{
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/5] rust: Fix the typos in doc
2025-05-20 15:27 [PATCH 0/5] hpet, rust: miscellaneous cleanup Zhao Liu
` (3 preceding siblings ...)
2025-05-20 15:27 ` [PATCH 4/5] rust: Fix Zhao's email address Zhao Liu
@ 2025-05-20 15:27 ` Zhao Liu
2025-05-20 15:43 ` Peter Maydell
4 siblings, 1 reply; 10+ messages in thread
From: Zhao Liu @ 2025-05-20 15:27 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, qemu-rust, Dapeng Mi, Zhao Liu
These typos are found by "cargo spellcheck". Though it outputs a lot of
noise and false positives, there still are some real typos.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Note: But I have to admit, cargo spellcheck isn't a great tool.
Picked from <20250218092108.3347963-1-zhao1.liu@intel.com> with checking
again.
---
rust/hw/char/pl011/src/device.rs | 4 ++--
rust/qemu-api/src/qom.rs | 4 ++--
rust/qemu-api/src/vmstate.rs | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index bde3be65c5b0..bd5cee046473 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -480,13 +480,13 @@ pub fn post_load(&mut self) -> Result<(), ()> {
}
impl PL011State {
- /// Initializes a pre-allocated, unitialized instance of `PL011State`.
+ /// Initializes a pre-allocated, uninitialized instance of `PL011State`.
///
/// # Safety
///
/// `self` must point to a correctly sized and aligned location for the
/// `PL011State` type. It must not be called more than once on the same
- /// location/instance. All its fields are expected to hold unitialized
+ /// location/instance. All its fields are expected to hold uninitialized
/// values with the sole exception of `parent_obj`.
unsafe fn init(&mut self) {
static PL011_OPS: MemoryRegionOps<PL011State> = MemoryRegionOpsBuilder::<PL011State>::new()
diff --git a/rust/qemu-api/src/qom.rs b/rust/qemu-api/src/qom.rs
index 41e5a5e29a82..14f98fee60ab 100644
--- a/rust/qemu-api/src/qom.rs
+++ b/rust/qemu-api/src/qom.rs
@@ -291,7 +291,7 @@ fn as_object(&self) -> &Object {
}
/// Return the receiver as a const raw pointer to Object.
- /// This is preferrable to `as_object_mut_ptr()` if a C
+ /// This is preferable to `as_object_mut_ptr()` if a C
/// function only needs a `const Object *`.
fn as_object_ptr(&self) -> *const bindings::Object {
self.as_object().as_ptr()
@@ -485,7 +485,7 @@ pub trait ObjectImpl: ObjectType + IsA<Object> {
/// `INSTANCE_INIT` functions have been called.
const INSTANCE_POST_INIT: Option<fn(&Self)> = None;
- /// Called on descendent classes after all parent class initialization
+ /// Called on descendant classes after all parent class initialization
/// has occurred, but before the class itself is initialized. This
/// is only useful if a class is not a leaf, and can be used to undo
/// the effects of copying the contents of the parent's class struct
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index 9c8b2398e9d4..812f390d7802 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -9,7 +9,7 @@
//! * [`vmstate_unused!`](crate::vmstate_unused) and
//! [`vmstate_of!`](crate::vmstate_of), which are used to express the
//! migration format for a struct. This is based on the [`VMState`] trait,
-//! which is defined by all migrateable types.
+//! which is defined by all migratable types.
//!
//! * [`impl_vmstate_forward`](crate::impl_vmstate_forward) and
//! [`impl_vmstate_bitsized`](crate::impl_vmstate_bitsized), which help with
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 5/5] rust: Fix the typos in doc
2025-05-20 15:27 ` [PATCH 5/5] rust: Fix the typos in doc Zhao Liu
@ 2025-05-20 15:43 ` Peter Maydell
0 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2025-05-20 15:43 UTC (permalink / raw)
To: Zhao Liu; +Cc: Paolo Bonzini, qemu-devel, qemu-rust, Dapeng Mi
On Tue, 20 May 2025 at 16:07, Zhao Liu <zhao1.liu@intel.com> wrote:
>
> These typos are found by "cargo spellcheck". Though it outputs a lot of
> noise and false positives, there still are some real typos.
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> Note: But I have to admit, cargo spellcheck isn't a great tool.
>
> Picked from <20250218092108.3347963-1-zhao1.liu@intel.com> with checking
> again.
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread