[PULL 05/27] docs: simplify DiamondRapids CPU docs

["Daniel P. Berrangé" <berrange@redhat.com>]

This aligns the first line of the docs with the style used for previous
CPU models, and simplifies the text in the remaining docs.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
---
 docs/system/cpu-models-x86.rst.inc | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc
index 3605d05a8c..126c5a1972 100644
--- a/docs/system/cpu-models-x86.rst.inc
+++ b/docs/system/cpu-models-x86.rst.inc
@@ -72,17 +72,13 @@ compatibility is required, use the newest CPU model that is compatible
 across all desired hosts.
 
 ``DiamondRapids``
-    Intel Xeon Processor.
+    Intel Xeon Processor (DiamondRapids, 2026)
 
-    Diamond Rapids product has a topology which differs from previous Xeon
-    products. It does not support SMT, but instead features a dual core
-    module (DCM) architecture. It also has core building blocks (CBB - die
-    level in CPU topology). The cache hierarchy is organized as follows:
-    L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per
-    CBB. This cache topology can be emulated for DiamondRapids CPU model
-    using the smp-cache configuration as shown below:
-
-    Example:
+    This does not include SMT but allows the module (dual core module
+    - DCM) and die (core building block - CBB) topology levels. The
+    cache hierarchy is L1 i/d cache per thread, L2 cache per module,
+    and L3 cache per die, which can be emulated using the smp-cache
+    option:
 
         ::
 
-- 
2.53.0