Re: [PATCH 2/2] rust/hpet: add trace events

[Manos Pitsidianakis <manos.pitsidianakis@linaro.org>]

On Sun, Nov 9, 2025 at 3:57 PM Stefan Hajnoczi <stefanha@redhat.com> wrote:
>
> Implement the same trace events as the C implementation.
>
> Notes:
> - Keep order of hpet_ram_write_invalid_tn_cmp and hpet_ram_write_tn_cmp
>   the same as the C implementation.
> - Put hpet_ram_write_timer_id in HPETTimer::write() instead of
>   HPETState::decode() so that reads can be excluded.
>
> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
> ---

LGTM but let's see what Zhao has to say also.

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  rust/hw/timer/hpet/Cargo.toml    |  1 +
>  rust/hw/timer/hpet/meson.build   |  1 +
>  rust/hw/timer/hpet/src/device.rs | 45 +++++++++++++++++++-------------
>  3 files changed, 29 insertions(+), 18 deletions(-)
>
> diff --git a/rust/hw/timer/hpet/Cargo.toml b/rust/hw/timer/hpet/Cargo.toml
> index f781b28d8b..5567eefda4 100644
> --- a/rust/hw/timer/hpet/Cargo.toml
> +++ b/rust/hw/timer/hpet/Cargo.toml
> @@ -18,6 +18,7 @@ bql = { path = "../../../bql" }
>  qom = { path = "../../../qom" }
>  system = { path = "../../../system" }
>  hwcore = { path = "../../../hw/core" }
> +trace = { path = "../../../trace" }
>
>  [lints]
>  workspace = true
> diff --git a/rust/hw/timer/hpet/meson.build b/rust/hw/timer/hpet/meson.build
> index bb64b96672..465995bb5a 100644
> --- a/rust/hw/timer/hpet/meson.build
> +++ b/rust/hw/timer/hpet/meson.build
> @@ -11,6 +11,7 @@ _libhpet_rs = static_library(
>      qom_rs,
>      system_rs,
>      hwcore_rs,
> +    trace_rs
>    ],
>  )
>
> diff --git a/rust/hw/timer/hpet/src/device.rs b/rust/hw/timer/hpet/src/device.rs
> index 3564aa79c6..90b0ae927c 100644
> --- a/rust/hw/timer/hpet/src/device.rs
> +++ b/rust/hw/timer/hpet/src/device.rs
> @@ -32,6 +32,8 @@
>
>  use crate::fw_cfg::HPETFwConfig;
>
> +::trace::include_trace!("hw_timer");
> +
>  /// Register space for each timer block (`HPET_BASE` is defined in hpet.h).
>  const HPET_REG_SPACE_LEN: u64 = 0x400; // 1024 bytes
>
> @@ -402,7 +404,8 @@ fn del_timer(&mut self) {
>
>      /// Configuration and Capability Register
>      fn set_tn_cfg_reg(&mut self, shift: u32, len: u32, val: u64) {
> -        // TODO: Add trace point - trace_hpet_ram_write_tn_cfg(addr & 4)
> +        trace::trace_hpet_ram_write_tn_cfg((shift / 8).try_into().unwrap());
> +
>          let old_val: u64 = self.config;
>          let mut new_val: u64 = old_val.deposit(shift, len, val);
>          new_val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
> @@ -435,17 +438,18 @@ fn set_tn_cmp_reg(&mut self, shift: u32, len: u32, val: u64) {
>          let mut length = len;
>          let mut value = val;
>
> -        // TODO: Add trace point - trace_hpet_ram_write_tn_cmp(addr & 4)
>          if self.is_32bit_mod() {
>              // High 32-bits are zero, leave them untouched.
>              if shift != 0 {
> -                // TODO: Add trace point - trace_hpet_ram_write_invalid_tn_cmp()
> +                trace::trace_hpet_ram_write_invalid_tn_cmp();
>                  return;
>              }
>              length = 64;
>              value = u64::from(value as u32); // truncate!
>          }
>
> +        trace::trace_hpet_ram_write_tn_cmp((shift / 8).try_into().unwrap());
> +
>          if !self.is_periodic() || self.is_valset_enabled() {
>              self.cmp = self.cmp.deposit(shift, length, value);
>          }
> @@ -512,6 +516,9 @@ const fn read(&self, reg: TimerRegister) -> u64 {
>
>      fn write(&mut self, reg: TimerRegister, value: u64, shift: u32, len: u32) {
>          use TimerRegister::*;
> +
> +        trace::trace_hpet_ram_write_timer_id(self.index as u64);
> +
>          match reg {
>              CFG => self.set_tn_cfg_reg(shift, len, value),
>              CMP => self.set_tn_cmp_reg(shift, len, value),
> @@ -689,15 +696,13 @@ fn set_int_status_reg(&self, shift: u32, _len: u32, val: u64) {
>      /// Main Counter Value Register
>      fn set_counter_reg(&self, shift: u32, len: u32, val: u64) {
>          if self.is_hpet_enabled() {
> -            // TODO: Add trace point -
> -            // trace_hpet_ram_write_counter_write_while_enabled()
> -            //
>              // HPET spec says that writes to this register should only be
>              // done while the counter is halted. So this is an undefined
>              // behavior. There's no need to forbid it, but when HPET is
>              // enabled, the changed counter value will not affect the
>              // tick count (i.e., the previously calculated offset will
>              // not be changed as well).
> +            trace::trace_hpet_ram_write_counter_write_while_enabled();
>          }
>          self.counter
>              .set(self.counter.get().deposit(shift, len, val));
> @@ -787,11 +792,10 @@ fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode<'_> {
>          } else {
>              let timer_id: usize = ((addr - 0x100) / 0x20) as usize;
>              if timer_id < self.num_timers {
> -                // TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id)
>                  TimerRegister::try_from(addr & 0x18)
>                      .map(|reg| HPETRegister::Timer(&self.timers[timer_id], reg))
>              } else {
> -                // TODO: Add trace point -  trace_hpet_timer_id_out_of_range(timer_id)
> +                trace::trace_hpet_timer_id_out_of_range(timer_id.try_into().unwrap());
>                  Err(addr)
>              }
>          };
> @@ -803,7 +807,8 @@ fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode<'_> {
>      }
>
>      fn read(&self, addr: hwaddr, size: u32) -> u64 {
> -        // TODO: Add trace point - trace_hpet_ram_read(addr)
> +        trace::trace_hpet_ram_read(addr);
> +
>          let HPETAddrDecode { shift, reg, .. } = self.decode(addr, size);
>
>          use GlobalRegister::*;
> @@ -814,16 +819,21 @@ fn read(&self, addr: hwaddr, size: u32) -> u64 {
>              Global(CFG) => self.config.get(),
>              Global(INT_STATUS) => self.int_status.get(),
>              Global(COUNTER) => {
> -                // TODO: Add trace point
> -                // trace_hpet_ram_read_reading_counter(addr & 4, cur_tick)
> -                if self.is_hpet_enabled() {
> +                let cur_tick = if self.is_hpet_enabled() {
>                      self.get_ticks()
>                  } else {
>                      self.counter.get()
> -                }
> +                };
> +
> +                trace::trace_hpet_ram_read_reading_counter(
> +                    (addr & 4) as u8,
> +                    cur_tick
> +                );
> +
> +                cur_tick
>              }
>              Unknown(_) => {
> -                // TODO: Add trace point- trace_hpet_ram_read_invalid()
> +                trace::trace_hpet_ram_read_invalid();
>                  0
>              }
>          }) >> shift
> @@ -832,7 +842,8 @@ fn read(&self, addr: hwaddr, size: u32) -> u64 {
>      fn write(&self, addr: hwaddr, value: u64, size: u32) {
>          let HPETAddrDecode { shift, len, reg } = self.decode(addr, size);
>
> -        // TODO: Add trace point - trace_hpet_ram_write(addr, value)
> +        trace::trace_hpet_ram_write(addr, value);
> +
>          use GlobalRegister::*;
>          use HPETRegister::*;
>          match reg {
> @@ -841,9 +852,7 @@ fn write(&self, addr: hwaddr, value: u64, size: u32) {
>              Global(CFG) => self.set_cfg_reg(shift, len, value),
>              Global(INT_STATUS) => self.set_int_status_reg(shift, len, value),
>              Global(COUNTER) => self.set_counter_reg(shift, len, value),
> -            Unknown(_) => {
> -                // TODO: Add trace point - trace_hpet_ram_write_invalid()
> -            }
> +            Unknown(_) => trace::trace_hpet_ram_write_invalid(),
>          }
>      }
>
> --
> 2.51.1
>