From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3135CCFA13 for ; Mon, 10 Nov 2025 14:00:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vISR4-0002vF-Br; Mon, 10 Nov 2025 08:59:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vISMI-0007uu-2u for qemu-rust@nongnu.org; Mon, 10 Nov 2025 08:55:04 -0500 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vISME-0006uo-6A for qemu-rust@nongnu.org; Mon, 10 Nov 2025 08:55:01 -0500 Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-640f4b6836bso5576731a12.3 for ; Mon, 10 Nov 2025 05:54:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1762782896; x=1763387696; darn=nongnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=wa+kuJOu0h++TrjcxztXc/AK43K6/9Cimfh1mrzlijk=; b=NrbSfvjh76JiWoC6ISjyRCoxllLNY5Pd3TWQi7ahQkanv75YOv6caCcNlELiu+Kfix uJrSOhuKlqDG8dcGjzzlXMuDtfY1eGKCBZH8VUrZ1CL79gvkILplDOPvAf8FT+VbeUKQ olRE4QyeS51ozoCAX/DLWdm4IAGuiuSSlYiA+Ve97V7IczI3G/B1JNoRzOse5hL+Kpyg wxPyaR3LQlxyuWZ5D/iGsD6lq7UviEKeH6ScKar1kKcHBM5EoJNccR60mjrHFOCZr6nN vu5Aaby4+2cjtuB+ZMJDyeliotwXspCi30mRh7RFdeb9ZJ1w99fbF/6g1+ya0cLt8xcI /E2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762782896; x=1763387696; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wa+kuJOu0h++TrjcxztXc/AK43K6/9Cimfh1mrzlijk=; b=Nm8iIlswEXqHp49EWlRGmLHOnM6iao9JSX+fMfsDbCyYaqzjpySISsta/RW94WEGIV aFFfHQI4uEu3jm1+Og1GOwuXU5Zogr1zzHerY8pmqFJgnuaGrTUpY7v5w39lk8pEANm/ QO8GaYpRlJ4Htv9CrM/frolD+9EZQg3F6k3wXkUIRl+WyBGnmXyuripd6sLChNtYA7+N AfJYCiTXwltGMvjQJ2QiPvWRjubdixgdYDTTe5wD1kTCCPSdsa3bURF/v27IEVhWbyIW h83u4mOtf2MNkcPSxqo6Hpo+x1WA6Gdx5sq6fcP2Sj7JbvyV+93b93gKLrTofrWCQRBS k6sQ== X-Forwarded-Encrypted: i=1; AJvYcCVhQa6RuVkr9loElJGVbPhgD3Bh9C0TgaSEJUE7t7WTRJz0Nq++xrAWyk7mEw+Nm6WLo4l/aQcTfOg=@nongnu.org X-Gm-Message-State: AOJu0Yy7hFJSF9aLbtdbZkR7wJ7pLw+i8D213bfhu8V+l1V6lp+2MFzW /GfbCt2oZhZKR+mVHnwaC7S9ecGDyTGCMVkfjukWx6l46AU73SNQxBOrNR8Jfb/3udNb5Sq6abr HgLfM5fgWnUfXztDnJQsbzFc1PxAAEiD1JulaDy4ADA== X-Gm-Gg: ASbGncvoqlY3asQb3iqKr8AqPs/INI97I0seQglDbFtE22Vv+H24ZjzrsT0ajiv5pD4 mf1LWYpGUsnYoJHKNpToAIq25NvEqi/pRnyaD5kShi97XXTU1haI+Ff56ex6KC97r8oi4aoQ8dg yNiIw6//rQ46qZ3C3+GJWnf5Qk9qcRExTXPlfdrWsgcf1EWW4c4ybJi0vK3+z7gJpx2pDgukgq9 uJE1I/LFNlL0eDPhA3liKW/mzN63+ViGKQJMN+xY24ucEUWTq8H+zBEf/QcTLHkgPSV X-Google-Smtp-Source: AGHT+IHexwgYS9uaq85sLmruf+NGdyV+asIeuqKhxuaFRrQH2lUQPryWX00dYirIEOa0Tsap8gexLN7NFmWclvFNEIc= X-Received: by 2002:a17:907:96a4:b0:b04:aadd:b8d7 with SMTP id a640c23a62f3a-b72e0285d38mr784107866b.13.1762782896289; Mon, 10 Nov 2025 05:54:56 -0800 (PST) MIME-Version: 1.0 References: <20251106215606.36598-1-stefanha@redhat.com> <20251106215606.36598-3-stefanha@redhat.com> In-Reply-To: <20251106215606.36598-3-stefanha@redhat.com> From: Manos Pitsidianakis Date: Mon, 10 Nov 2025 15:54:29 +0200 X-Gm-Features: AWmQ_blMYXlLBTBO7IQqFFZejGhw1RKk48Dj6ANS_TVVyaYgKOFxPBdDKoKhisk Message-ID: Subject: Re: [PATCH 2/2] rust/hpet: add trace events To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Zhao Liu , Paolo Bonzini , qemu-rust@nongnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-rust@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: QEMU Rust-related patches and discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-rust-bounces+qemu-rust=archiver.kernel.org@nongnu.org Sender: qemu-rust-bounces+qemu-rust=archiver.kernel.org@nongnu.org On Sun, Nov 9, 2025 at 3:57=E2=80=AFPM Stefan Hajnoczi wrote: > > Implement the same trace events as the C implementation. > > Notes: > - Keep order of hpet_ram_write_invalid_tn_cmp and hpet_ram_write_tn_cmp > the same as the C implementation. > - Put hpet_ram_write_timer_id in HPETTimer::write() instead of > HPETState::decode() so that reads can be excluded. > > Signed-off-by: Stefan Hajnoczi > --- LGTM but let's see what Zhao has to say also. Reviewed-by: Manos Pitsidianakis > rust/hw/timer/hpet/Cargo.toml | 1 + > rust/hw/timer/hpet/meson.build | 1 + > rust/hw/timer/hpet/src/device.rs | 45 +++++++++++++++++++------------- > 3 files changed, 29 insertions(+), 18 deletions(-) > > diff --git a/rust/hw/timer/hpet/Cargo.toml b/rust/hw/timer/hpet/Cargo.tom= l > index f781b28d8b..5567eefda4 100644 > --- a/rust/hw/timer/hpet/Cargo.toml > +++ b/rust/hw/timer/hpet/Cargo.toml > @@ -18,6 +18,7 @@ bql =3D { path =3D "../../../bql" } > qom =3D { path =3D "../../../qom" } > system =3D { path =3D "../../../system" } > hwcore =3D { path =3D "../../../hw/core" } > +trace =3D { path =3D "../../../trace" } > > [lints] > workspace =3D true > diff --git a/rust/hw/timer/hpet/meson.build b/rust/hw/timer/hpet/meson.bu= ild > index bb64b96672..465995bb5a 100644 > --- a/rust/hw/timer/hpet/meson.build > +++ b/rust/hw/timer/hpet/meson.build > @@ -11,6 +11,7 @@ _libhpet_rs =3D static_library( > qom_rs, > system_rs, > hwcore_rs, > + trace_rs > ], > ) > > diff --git a/rust/hw/timer/hpet/src/device.rs b/rust/hw/timer/hpet/src/de= vice.rs > index 3564aa79c6..90b0ae927c 100644 > --- a/rust/hw/timer/hpet/src/device.rs > +++ b/rust/hw/timer/hpet/src/device.rs > @@ -32,6 +32,8 @@ > > use crate::fw_cfg::HPETFwConfig; > > +::trace::include_trace!("hw_timer"); > + > /// Register space for each timer block (`HPET_BASE` is defined in hpet.= h). > const HPET_REG_SPACE_LEN: u64 =3D 0x400; // 1024 bytes > > @@ -402,7 +404,8 @@ fn del_timer(&mut self) { > > /// Configuration and Capability Register > fn set_tn_cfg_reg(&mut self, shift: u32, len: u32, val: u64) { > - // TODO: Add trace point - trace_hpet_ram_write_tn_cfg(addr & 4) > + trace::trace_hpet_ram_write_tn_cfg((shift / 8).try_into().unwrap= ()); > + > let old_val: u64 =3D self.config; > let mut new_val: u64 =3D old_val.deposit(shift, len, val); > new_val =3D hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_M= ASK); > @@ -435,17 +438,18 @@ fn set_tn_cmp_reg(&mut self, shift: u32, len: u32, = val: u64) { > let mut length =3D len; > let mut value =3D val; > > - // TODO: Add trace point - trace_hpet_ram_write_tn_cmp(addr & 4) > if self.is_32bit_mod() { > // High 32-bits are zero, leave them untouched. > if shift !=3D 0 { > - // TODO: Add trace point - trace_hpet_ram_write_invalid_= tn_cmp() > + trace::trace_hpet_ram_write_invalid_tn_cmp(); > return; > } > length =3D 64; > value =3D u64::from(value as u32); // truncate! > } > > + trace::trace_hpet_ram_write_tn_cmp((shift / 8).try_into().unwrap= ()); > + > if !self.is_periodic() || self.is_valset_enabled() { > self.cmp =3D self.cmp.deposit(shift, length, value); > } > @@ -512,6 +516,9 @@ const fn read(&self, reg: TimerRegister) -> u64 { > > fn write(&mut self, reg: TimerRegister, value: u64, shift: u32, len:= u32) { > use TimerRegister::*; > + > + trace::trace_hpet_ram_write_timer_id(self.index as u64); > + > match reg { > CFG =3D> self.set_tn_cfg_reg(shift, len, value), > CMP =3D> self.set_tn_cmp_reg(shift, len, value), > @@ -689,15 +696,13 @@ fn set_int_status_reg(&self, shift: u32, _len: u32,= val: u64) { > /// Main Counter Value Register > fn set_counter_reg(&self, shift: u32, len: u32, val: u64) { > if self.is_hpet_enabled() { > - // TODO: Add trace point - > - // trace_hpet_ram_write_counter_write_while_enabled() > - // > // HPET spec says that writes to this register should only b= e > // done while the counter is halted. So this is an undefined > // behavior. There's no need to forbid it, but when HPET is > // enabled, the changed counter value will not affect the > // tick count (i.e., the previously calculated offset will > // not be changed as well). > + trace::trace_hpet_ram_write_counter_write_while_enabled(); > } > self.counter > .set(self.counter.get().deposit(shift, len, val)); > @@ -787,11 +792,10 @@ fn decode(&self, mut addr: hwaddr, size: u32) -> HP= ETAddrDecode<'_> { > } else { > let timer_id: usize =3D ((addr - 0x100) / 0x20) as usize; > if timer_id < self.num_timers { > - // TODO: Add trace point - trace_hpet_ram_[read|write]_t= imer_id(timer_id) > TimerRegister::try_from(addr & 0x18) > .map(|reg| HPETRegister::Timer(&self.timers[timer_id= ], reg)) > } else { > - // TODO: Add trace point - trace_hpet_timer_id_out_of_r= ange(timer_id) > + trace::trace_hpet_timer_id_out_of_range(timer_id.try_int= o().unwrap()); > Err(addr) > } > }; > @@ -803,7 +807,8 @@ fn decode(&self, mut addr: hwaddr, size: u32) -> HPET= AddrDecode<'_> { > } > > fn read(&self, addr: hwaddr, size: u32) -> u64 { > - // TODO: Add trace point - trace_hpet_ram_read(addr) > + trace::trace_hpet_ram_read(addr); > + > let HPETAddrDecode { shift, reg, .. } =3D self.decode(addr, size= ); > > use GlobalRegister::*; > @@ -814,16 +819,21 @@ fn read(&self, addr: hwaddr, size: u32) -> u64 { > Global(CFG) =3D> self.config.get(), > Global(INT_STATUS) =3D> self.int_status.get(), > Global(COUNTER) =3D> { > - // TODO: Add trace point > - // trace_hpet_ram_read_reading_counter(addr & 4, cur_tic= k) > - if self.is_hpet_enabled() { > + let cur_tick =3D if self.is_hpet_enabled() { > self.get_ticks() > } else { > self.counter.get() > - } > + }; > + > + trace::trace_hpet_ram_read_reading_counter( > + (addr & 4) as u8, > + cur_tick > + ); > + > + cur_tick > } > Unknown(_) =3D> { > - // TODO: Add trace point- trace_hpet_ram_read_invalid() > + trace::trace_hpet_ram_read_invalid(); > 0 > } > }) >> shift > @@ -832,7 +842,8 @@ fn read(&self, addr: hwaddr, size: u32) -> u64 { > fn write(&self, addr: hwaddr, value: u64, size: u32) { > let HPETAddrDecode { shift, len, reg } =3D self.decode(addr, siz= e); > > - // TODO: Add trace point - trace_hpet_ram_write(addr, value) > + trace::trace_hpet_ram_write(addr, value); > + > use GlobalRegister::*; > use HPETRegister::*; > match reg { > @@ -841,9 +852,7 @@ fn write(&self, addr: hwaddr, value: u64, size: u32) = { > Global(CFG) =3D> self.set_cfg_reg(shift, len, value), > Global(INT_STATUS) =3D> self.set_int_status_reg(shift, len, = value), > Global(COUNTER) =3D> self.set_counter_reg(shift, len, value)= , > - Unknown(_) =3D> { > - // TODO: Add trace point - trace_hpet_ram_write_invalid(= ) > - } > + Unknown(_) =3D> trace::trace_hpet_ram_write_invalid(), > } > } > > -- > 2.51.1 >