[Qemu-trivial] [PATCH] arm-dis: Fix spelling in comments (iff -> if)

[Stefan Weil <sw@weilnetz.de>]

The spelling 'iff' is sometimes used for 'if and only if'.
Even if that meaning could be applied here, it is not used
consistently. It is also quite unusual to use 'if and only if'
in technical documentation. Therefore a simple 'if' should be
preferred here.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
---
 arm-dis.c |   22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arm-dis.c b/arm-dis.c
index 6bc4d71..db15eca 100644
--- a/arm-dis.c
+++ b/arm-dis.c
@@ -130,8 +130,8 @@ struct opcode16
    %z<code>		print a double precision VFP reg
 			  Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 
-   %<bitfield>'c	print specified char iff bitfield is all ones
-   %<bitfield>`c	print specified char iff bitfield is all zeroes
+   %<bitfield>'c	print specified char if bitfield is all ones
+   %<bitfield>`c	print specified char if bitfield is all zeroes
    %<bitfield>?ab...    select from array of values in big endian order
 
    %L			print as an iWMMXt N/M width field.
@@ -522,8 +522,8 @@ static const struct opcode32 coprocessor_opcodes[] =
    %<bitfield>Tn	print short scaled width limited by n
    %<bitfield>Un	print long scaled width limited by n
 
-   %<bitfield>'c	print specified char iff bitfield is all ones
-   %<bitfield>`c	print specified char iff bitfield is all zeroes
+   %<bitfield>'c	print specified char if bitfield is all ones
+   %<bitfield>`c	print specified char if bitfield is all zeroes
    %<bitfield>?ab...    select from array of values in big endian order  */
 
 static const struct opcode32 neon_opcodes[] =
@@ -787,8 +787,8 @@ static const struct opcode32 neon_opcodes[] =
    %c			print condition code (always bits 28-31)
    %m			print register mask for ldm/stm instruction
    %o			print operand2 (immediate or register + shift)
-   %p			print 'p' iff bits 12-15 are 15
-   %t			print 't' iff bit 21 set and bit 24 clear
+   %p			print 'p' if bits 12-15 are 15
+   %t			print 't' if bit 21 set and bit 24 clear
    %B			print arm BLX(1) destination
    %C			print the PSR sub type.
    %U			print barrier type.
@@ -800,8 +800,8 @@ static const struct opcode32 neon_opcodes[] =
    %<bitfield>x		print the bitfield in hex
    %<bitfield>X		print the bitfield as 1 hex digit without leading "0x"
 
-   %<bitfield>'c	print specified char iff bitfield is all ones
-   %<bitfield>`c	print specified char iff bitfield is all zeroes
+   %<bitfield>'c	print specified char if bitfield is all ones
+   %<bitfield>`c	print specified char if bitfield is all zeroes
    %<bitfield>?ab...    select from array of values in big endian order
 
    %e                   print arm SMI operand (bits 0..7,8..19).
@@ -1090,7 +1090,7 @@ static const struct opcode32 arm_opcodes[] =
    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
    %<bitfield>B         print Thumb branch destination (signed displacement)
    %<bitfield>c         print bitfield as a condition code
-   %<bitnum>'c		print specified char iff bit is one
+   %<bitnum>'c		print specified char if bit is one
    %<bitnum>?ab		print a if bit is one else print b.  */
 
 static const struct opcode16 thumb_opcodes[] =
@@ -1248,8 +1248,8 @@ static const struct opcode16 thumb_opcodes[] =
        %<bitfield>r	print bitfield as an ARM register
        %<bitfield>c	print bitfield as a condition code
 
-       %<bitfield>'c	print specified char iff bitfield is all ones
-       %<bitfield>`c	print specified char iff bitfield is all zeroes
+       %<bitfield>'c	print specified char if bitfield is all ones
+       %<bitfield>`c	print specified char if bitfield is all zeroes
        %<bitfield>?ab... select from array of values in big endian order
 
    With one exception at the bottom (done because BL and BLX(1) need
-- 
1.7.9