[PATCH v4 0/2] gpu: nova-core: gsp: fix undefined behavior in command queue code

Alexandre Courbot
2026-04-01T14:30:02Z

This revision is mostly to fix the testbot build failures of v3. They
were due to the inability of the compiler optimizer to preserve the
invariant that `rx == 0` in `driver_write_area`. To preserve it, a
nested branch is used, and the methods providing the range invariants
are made inline defensively.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
Changes in v4:
- Make some methods providing the `ptr_project!` invariants inline.
- Use code paths that preserve the invariants `ptr_project!` depends on
more obviously to fix these testbot build failures:
- https://lore.kernel.org/all/202603280326.ucDKVaf2-lkp@intel.com/
- https://lore.kernel.org/all/202603281331.1ESuqgfz-lkp@intel.com/
- Improve safety comment when creating the mutable slices (thanks Danilo!).
- Link to v3: https://patch.msgid.link/20260326-cmdq-ub-fix-v3-1-96af2148ca5c@nvidia.com

Changes in v3:
- Rebase on top of latest `drm-rust-next` (with `Coherent` patches).
- Use pointer projections. (thanks Gary!)
- Link to v2: https://patch.msgid.link/20260323-cmdq-ub-fix-v2-1-77d1213c3f7f@nvidia.com

Changes in v2:
- Use `u32_as_usize` consistently.
- Reduce the number of `unsafe` blocks by computing the end offset of
the returned slices and creating them at the end, in one step.
- Take advantage of the fact that both slices have the same start index
regardless of the branch chosen.
- Improve safety comments.
- Link to v1: https://patch.msgid.link/20260319-cmdq-ub-fix-v1-1-0f9f6e8f3ce3@nvidia.com

---
Alexandre Courbot (2):
gpu: nova-core: gsp: inline methods providing queue range invariants
gpu: nova-core: gsp: fix undefined behavior in command queue code

drivers/gpu/nova-core/gsp/cmdq.rs | 118 ++++++++++++++++++++++----------------
drivers/gpu/nova-core/gsp/fw.rs | 4 ++
2 files changed, 73 insertions(+), 49 deletions(-)
---
base-commit: 7c50d748b4a635bc39802ea3f6b120e66b1b9067
change-id: 20260319-cmdq-ub-fix-d57b09a745b9

Best regards,
--
Alexandre Courbot <acourbot@nvidia.com>