From: Andrew Lunn <andrew@lunn.ch>
To: Benno Lossin <benno.lossin@proton.me>
Cc: FUJITA Tomonori <fujita.tomonori@gmail.com>,
netdev@vger.kernel.org, rust-for-linux@vger.kernel.org,
miguel.ojeda.sandonis@gmail.com, tmgross@umich.edu,
boqun.feng@gmail.com, wedsonaf@gmail.com, greg@kroah.com
Subject: Re: [PATCH net-next v4 1/4] rust: core abstractions for network PHY drivers
Date: Tue, 17 Oct 2023 14:38:31 +0200 [thread overview]
Message-ID: <1454c3e6-82d1-4f60-b07d-bc3b47b23662@lunn.ch> (raw)
In-Reply-To: <98471d44-c267-4c80-ba54-82ab2563e465@proton.me>
> > Because set_speed() updates the member in phy_device and read()
> > updates the object that phy_device points to?
>
> `set_speed` is entirely implemented on the Rust side and is not protected
> by a lock.
With the current driver, all entry points into the driver are called
from the phylib core, and the core guarantees that the lock is
taken. So it should not matter if its entirely implemented in the Rust
side, somewhere up the call stack, the lock was taken.
> >> What about these functions?
> >> - resolve_aneg_linkmode
> >> - genphy_soft_reset
> >> - init_hw
> >> - start_aneg
> >> - genphy_read_status
> >> - genphy_update_link
> >> - genphy_read_lpa
> >> - genphy_read_abilities
> >
> > As Andrew replied, all the functions update some member in phy_device.
>
> Do all of these functions lock the `bus->mdio_lock`?
When accessing the hardware, yes.
The basic architecture is that at the bottom we have an MDIO bus, and
on top of that bus, we have a number of devices. The MDIO core will
serialise access to the bus, so only one device on the bus can be
accessed at once. The phylib core will serialise access to the PHY,
but when there are multiple PHYs, the phylib core will allow parallel
access to different PHYs.
In summary, the core of each layer protects the drivers using that
layer from multiple parallel accesses from above.
Andrew
next prev parent reply other threads:[~2023-10-17 12:38 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-12 12:53 [PATCH net-next v4 0/4] Rust abstractions for network PHY drivers FUJITA Tomonori
2023-10-12 12:53 ` [PATCH net-next v4 1/4] rust: core " FUJITA Tomonori
2023-10-13 21:31 ` Benno Lossin
2023-10-14 2:12 ` Andrew Lunn
2023-10-14 4:50 ` FUJITA Tomonori
2023-10-14 17:00 ` Miguel Ojeda
2023-10-14 23:18 ` FUJITA Tomonori
2023-10-15 15:47 ` Andrew Lunn
2023-10-14 7:22 ` FUJITA Tomonori
2023-10-14 8:07 ` Benno Lossin
2023-10-14 10:32 ` FUJITA Tomonori
2023-10-14 14:54 ` Benno Lossin
2023-10-14 15:53 ` Boqun Feng
2023-10-14 16:15 ` FUJITA Tomonori
2023-10-14 17:07 ` Benno Lossin
2023-10-14 21:18 ` Andrew Lunn
2023-10-14 22:39 ` FUJITA Tomonori
2023-10-17 7:06 ` Benno Lossin
2023-10-17 7:32 ` FUJITA Tomonori
2023-10-17 7:41 ` Benno Lossin
2023-10-17 11:32 ` FUJITA Tomonori
2023-10-17 12:38 ` Andrew Lunn [this message]
2023-10-17 14:04 ` Benno Lossin
2023-10-17 14:21 ` Greg KH
2023-10-17 14:32 ` Benno Lossin
2023-10-17 15:17 ` Miguel Ojeda
2023-10-17 16:15 ` Greg KH
2023-10-17 16:13 ` Boqun Feng
2023-10-17 15:03 ` Miguel Ojeda
2023-10-14 12:00 ` Miguel Ojeda
2023-10-12 12:53 ` [PATCH net-next v4 2/4] rust: net::phy add module_phy_driver macro FUJITA Tomonori
2023-10-12 12:53 ` [PATCH net-next v4 3/4] MAINTAINERS: add Rust PHY abstractions to the ETHERNET PHY LIBRARY FUJITA Tomonori
2023-10-13 14:34 ` Boqun Feng
2023-10-13 15:24 ` FUJITA Tomonori
2023-10-13 16:10 ` Boqun Feng
2023-10-13 16:17 ` Trevor Gross
2023-10-13 18:43 ` Miguel Ojeda
2023-10-13 18:49 ` Andrew Lunn
2023-10-14 5:15 ` FUJITA Tomonori
2023-10-14 18:18 ` Miguel Ojeda
2023-10-12 12:53 ` [PATCH net-next v4 4/4] net: phy: add Rust Asix PHY driver FUJITA Tomonori
2023-10-14 6:01 ` FUJITA Tomonori
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