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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f258b4314sm27002426f8f.9.2025.02.22.14.12.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Feb 2025 14:12:52 -0800 (PST) Date: Sat, 22 Feb 2025 22:12:48 +0000 From: David Laight To: Kent Overstreet Cc: "H. Peter Anvin" , Linus Torvalds , Ventura Jack , Gary Guo , airlied@gmail.com, boqun.feng@gmail.com, ej@inai.de, gregkh@linuxfoundation.org, hch@infradead.org, ksummit@lists.linux.dev, linux-kernel@vger.kernel.org, miguel.ojeda.sandonis@gmail.com, rust-for-linux@vger.kernel.org Subject: Re: C aggregate passing (Rust kernel policy) Message-ID: <20250222221248.772b4bf6@pumpkin> In-Reply-To: References: <20250222141521.1fe24871@eugeo> <6pwjvkejyw2wjxobu6ffeyolkk2fppuuvyrzqpigchqzhclnhm@v5zhfpmirk2c> <6EFFB41B-9145-496E-8217-07AF404BE695@zytor.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Sat, 22 Feb 2025 16:22:08 -0500 Kent Overstreet wrote: > On Sat, Feb 22, 2025 at 12:54:31PM -0800, H. Peter Anvin wrote: > > VLIW and OoO might seem orthogonal, but they aren't =E2=80=93 because t= hey are > > trying to solve the same problem, combining them either means the OoO > > engine can't do a very good job because of false dependencies (if you > > are scheduling molecules) or you have to break them instructions down > > into atoms, at which point it is just a (often quite inefficient) RISC > > encoding. In short, VLIW *might* make sense when you are statically > > scheduling a known pipeline, but it is basically a dead end for > > evolution =E2=80=93 so unless you can JIT your code for each new chip > > generation... =20 >=20 > JITing for each chip generation would be a part of any serious new VLIW > effort. It's plenty doable in the open source world and the gains are > too big to ignore. Doesn't most code get 'dumbed down' to whatever 'normal' ABI compilers can easily handle. A few hot loops might get optimised, but most code won't be. Of course AI/GPU code is going to spend a lot of time in some tight loops. But no one is going to go through the TCP stack and optimise the source so that a compiler can make a better job of it for 'this years' cpu. For various reasons ended up writing a simple 32bit cpu last year (in VHDL = for an fgpa). The ALU is easy - just a big MUX. The difficulty is feeding the result of one instruction into the next. Normal code needs to do that all the time, you can't afford a stall (never mind the 3 clocks writing to/from the register 'memory' would take). In fact the ALU dependencies [1] ended up being slower than the instruction= fetch code, so I managed to take predicted and unconditional branches without a s= tall. So no point having the 'branch delay slot' of sparc32. [1] multiply was the issue, even with a pipeline stall if the result has ne= eded. In any case it only had to run at 62.5MHz (related to the PCIe speed). Was definitely an interesting exercise. David