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From: Deepak Gupta <debug@rivosinc.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Borislav Petkov" <bp@alien8.de>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	"Andrew Morton" <akpm@linux-foundation.org>,
	"Liam R. Howlett" <Liam.Howlett@oracle.com>,
	"Vlastimil Babka" <vbabka@suse.cz>,
	"Lorenzo Stoakes" <lorenzo.stoakes@oracle.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Conor Dooley" <conor@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Arnd Bergmann" <arnd@arndb.de>,
	"Christian Brauner" <brauner@kernel.org>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Oleg Nesterov" <oleg@redhat.com>,
	"Eric Biederman" <ebiederm@xmission.com>,
	"Kees Cook" <kees@kernel.org>, "Jonathan Corbet" <corbet@lwn.net>,
	"Shuah Khan" <shuah@kernel.org>, "Jann Horn" <jannh@google.com>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Miguel Ojeda" <ojeda@kernel.org>,
	"Alex Gaynor" <alex.gaynor@gmail.com>,
	"Boqun Feng" <boqun.feng@gmail.com>,
	"Gary Guo" <gary@garyguo.net>,
	"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
	"Andreas Hindborg" <a.hindborg@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"Trevor Gross" <tmgross@umich.edu>,
	"Benno Lossin" <lossin@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org,
	 linux-mm@kvack.org, linux-riscv@lists.infradead.org,
	 devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
	 linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
	 alistair.francis@wdc.com, richard.henderson@linaro.org,
	jim.shu@sifive.com,  andybnac@gmail.com, kito.cheng@sifive.com,
	charlie@rivosinc.com,  atishp@rivosinc.com, evan@rivosinc.com,
	cleger@rivosinc.com,  alexghiti@rivosinc.com,
	samitolvanen@google.com, broonie@kernel.org,
	 rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org,
	 Zong Li <zong.li@sifive.com>, Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v18 10/27] riscv/mm: Implement map_shadow_stack() syscall
Date: Fri, 11 Jul 2025 12:46:15 -0700	[thread overview]
Message-ID: <20250711-v5_user_cfi_series-v18-10-a8ee62f9f38e@rivosinc.com> (raw)
In-Reply-To: <20250711-v5_user_cfi_series-v18-0-a8ee62f9f38e@rivosinc.com>

As discussed extensively in the changelog for the addition of this
syscall on x86 ("x86/shstk: Introduce map_shadow_stack syscall") the
existing mmap() and madvise() syscalls do not map entirely well onto the
security requirements for shadow stack memory since they lead to windows
where memory is allocated but not yet protected or stacks which are not
properly and safely initialised. Instead a new syscall map_shadow_stack()
has been defined which allocates and initialises a shadow stack page.

This patch implements this syscall for riscv. riscv doesn't require token
to be setup by kernel because user mode can do that by itself. However to
provide compatibility and portability with other architectues, user mode
can specify token set flag.

Reviewed-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
 arch/riscv/kernel/Makefile  |   1 +
 arch/riscv/kernel/usercfi.c | 143 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 144 insertions(+)

diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index c7b542573407..0b245f36731e 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -125,3 +125,4 @@ obj-$(CONFIG_ACPI)		+= acpi.o
 obj-$(CONFIG_ACPI_NUMA)	+= acpi_numa.o
 
 obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) += bugs.o
+obj-$(CONFIG_RISCV_USER_CFI) += usercfi.o
diff --git a/arch/riscv/kernel/usercfi.c b/arch/riscv/kernel/usercfi.c
new file mode 100644
index 000000000000..0b3bbb41490a
--- /dev/null
+++ b/arch/riscv/kernel/usercfi.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Rivos, Inc.
+ * Deepak Gupta <debug@rivosinc.com>
+ */
+
+#include <linux/sched.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/uaccess.h>
+#include <linux/sizes.h>
+#include <linux/user.h>
+#include <linux/syscalls.h>
+#include <linux/prctl.h>
+#include <asm/csr.h>
+#include <asm/usercfi.h>
+
+#define SHSTK_ENTRY_SIZE sizeof(void *)
+
+/*
+ * Writes on shadow stack can either be `sspush` or `ssamoswap`. `sspush` can happen
+ * implicitly on current shadow stack pointed to by CSR_SSP. `ssamoswap` takes pointer to
+ * shadow stack. To keep it simple, we plan to use `ssamoswap` to perform writes on shadow
+ * stack.
+ */
+static noinline unsigned long amo_user_shstk(unsigned long *addr, unsigned long val)
+{
+	/*
+	 * Never expect -1 on shadow stack. Expect return addresses and zero
+	 */
+	unsigned long swap = -1;
+
+	__enable_user_access();
+	asm goto(
+		".option push\n"
+		".option arch, +zicfiss\n"
+		"1: ssamoswap.d %[swap], %[val], %[addr]\n"
+		_ASM_EXTABLE(1b, %l[fault])
+		".option pop\n"
+		: [swap] "=r" (swap), [addr] "+A" (*addr)
+		: [val] "r" (val)
+		: "memory"
+		: fault
+		);
+	__disable_user_access();
+	return swap;
+fault:
+	__disable_user_access();
+	return -1;
+}
+
+/*
+ * Create a restore token on the shadow stack.  A token is always XLEN wide
+ * and aligned to XLEN.
+ */
+static int create_rstor_token(unsigned long ssp, unsigned long *token_addr)
+{
+	unsigned long addr;
+
+	/* Token must be aligned */
+	if (!IS_ALIGNED(ssp, SHSTK_ENTRY_SIZE))
+		return -EINVAL;
+
+	/* On RISC-V we're constructing token to be function of address itself */
+	addr = ssp - SHSTK_ENTRY_SIZE;
+
+	if (amo_user_shstk((unsigned long __user *)addr, (unsigned long)ssp) == -1)
+		return -EFAULT;
+
+	if (token_addr)
+		*token_addr = addr;
+
+	return 0;
+}
+
+static unsigned long allocate_shadow_stack(unsigned long addr, unsigned long size,
+					   unsigned long token_offset, bool set_tok)
+{
+	int flags = MAP_ANONYMOUS | MAP_PRIVATE;
+	struct mm_struct *mm = current->mm;
+	unsigned long populate, tok_loc = 0;
+
+	if (addr)
+		flags |= MAP_FIXED_NOREPLACE;
+
+	mmap_write_lock(mm);
+	addr = do_mmap(NULL, addr, size, PROT_READ, flags,
+		       VM_SHADOW_STACK | VM_WRITE, 0, &populate, NULL);
+	mmap_write_unlock(mm);
+
+	if (!set_tok || IS_ERR_VALUE(addr))
+		goto out;
+
+	if (create_rstor_token(addr + token_offset, &tok_loc)) {
+		vm_munmap(addr, size);
+		return -EINVAL;
+	}
+
+	addr = tok_loc;
+
+out:
+	return addr;
+}
+
+SYSCALL_DEFINE3(map_shadow_stack, unsigned long, addr, unsigned long, size, unsigned int, flags)
+{
+	bool set_tok = flags & SHADOW_STACK_SET_TOKEN;
+	unsigned long aligned_size = 0;
+
+	if (!cpu_supports_shadow_stack())
+		return -EOPNOTSUPP;
+
+	/* Anything other than set token should result in invalid param */
+	if (flags & ~SHADOW_STACK_SET_TOKEN)
+		return -EINVAL;
+
+	/*
+	 * Unlike other architectures, on RISC-V, SSP pointer is held in CSR_SSP and is available
+	 * CSR in all modes. CSR accesses are performed using 12bit index programmed in instruction
+	 * itself. This provides static property on register programming and writes to CSR can't
+	 * be unintentional from programmer's perspective. As long as programmer has guarded areas
+	 * which perform writes to CSR_SSP properly, shadow stack pivoting is not possible. Since
+	 * CSR_SSP is writeable by user mode, it itself can setup a shadow stack token subsequent
+	 * to allocation. Although in order to provide portablity with other architecture (because
+	 * `map_shadow_stack` is arch agnostic syscall), RISC-V will follow expectation of a token
+	 * flag in flags and if provided in flags, setup a token at the base.
+	 */
+
+	/* If there isn't space for a token */
+	if (set_tok && size < SHSTK_ENTRY_SIZE)
+		return -ENOSPC;
+
+	if (addr && (addr & (PAGE_SIZE - 1)))
+		return -EINVAL;
+
+	aligned_size = PAGE_ALIGN(size);
+	if (aligned_size < size)
+		return -EOVERFLOW;
+
+	return allocate_shadow_stack(addr, aligned_size, size, set_tok);
+}

-- 
2.43.0


  parent reply	other threads:[~2025-07-11 19:46 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-11 19:46 [PATCH v18 00/27] riscv control-flow integrity for usermode Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 01/27] mm: VM_SHADOW_STACK definition for riscv Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 02/27] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 03/27] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 04/27] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 05/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 06/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 07/27] riscv/mm: manufacture shadow stack pte Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 08/27] riscv/mm: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 09/27] riscv/mm: write protect and shadow stack Deepak Gupta
2025-07-11 19:46 ` Deepak Gupta [this message]
2025-07-11 19:46 ` [PATCH v18 11/27] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 12/27] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 13/27] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 14/27] riscv: Implements arch agnostic indirect branch tracking prctls Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 15/27] riscv/traps: Introduce software check exception and uprobe handling Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 16/27] riscv: signal: abstract header saving for setup_sigcontext Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 17/27] riscv/signal: save and restore of shadow stack for signal Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 18/27] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 19/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 20/27] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 21/27] riscv: kernel command line option to opt out of user cfi Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 22/27] riscv: enable kernel access to shadow stack memory via FWFT sbi call Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 23/27] arch/riscv: compile vdso with landing pad and shadow stack note Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 24/27] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 25/27] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 26/27] riscv: Documentation for shadow stack on riscv Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 27/27] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
2025-07-11 20:25 ` [PATCH v18 00/27] riscv control-flow integrity for usermode Deepak Gupta

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