From: Deepak Gupta <debug@rivosinc.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Liam R. Howlett" <Liam.Howlett@oracle.com>,
"Vlastimil Babka" <vbabka@suse.cz>,
"Lorenzo Stoakes" <lorenzo.stoakes@oracle.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Arnd Bergmann" <arnd@arndb.de>,
"Christian Brauner" <brauner@kernel.org>,
"Peter Zijlstra" <peterz@infradead.org>,
"Oleg Nesterov" <oleg@redhat.com>,
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"Kees Cook" <kees@kernel.org>, "Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>, "Jann Horn" <jannh@google.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Miguel Ojeda" <ojeda@kernel.org>,
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"Alice Ryhl" <aliceryhl@google.com>,
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Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org,
linux-mm@kvack.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
alistair.francis@wdc.com, richard.henderson@linaro.org,
jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com,
charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com,
cleger@rivosinc.com, alexghiti@rivosinc.com,
samitolvanen@google.com, broonie@kernel.org,
rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org,
Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v18 19/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files
Date: Fri, 11 Jul 2025 12:46:24 -0700 [thread overview]
Message-ID: <20250711-v5_user_cfi_series-v18-19-a8ee62f9f38e@rivosinc.com> (raw)
In-Reply-To: <20250711-v5_user_cfi_series-v18-0-a8ee62f9f38e@rivosinc.com>
Expose a new register type NT_RISCV_USER_CFI for risc-v cfi status and
state. Intentionally both landing pad and shadow stack status and state
are rolled into cfi state. Creating two different NT_RISCV_USER_XXX would
not be useful and wastage of a note type. Enabling, disabling and locking
of feature is not allowed via ptrace set interface. However setting `elp`
state or setting shadow stack pointer are allowed via ptrace set interface
. It is expected `gdb` might have use to fixup `elp` state or `shadow
stack` pointer.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
arch/riscv/include/uapi/asm/ptrace.h | 30 ++++++++++++
arch/riscv/kernel/ptrace.c | 95 ++++++++++++++++++++++++++++++++++++
include/uapi/linux/elf.h | 2 +
3 files changed, 127 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h
index 659ea3af5680..63e18ee2e050 100644
--- a/arch/riscv/include/uapi/asm/ptrace.h
+++ b/arch/riscv/include/uapi/asm/ptrace.h
@@ -131,6 +131,36 @@ struct __sc_riscv_cfi_state {
unsigned long ss_ptr; /* shadow stack pointer */
};
+#define PTRACE_CFI_LP_EN_BIT 0
+#define PTRACE_CFI_LP_LOCK_BIT 1
+#define PTRACE_CFI_ELP_BIT 2
+#define PTRACE_CFI_SS_EN_BIT 3
+#define PTRACE_CFI_SS_LOCK_BIT 4
+#define PTRACE_CFI_SS_PTR_BIT 5
+
+#define PTRACE_CFI_LP_EN_STATE (1 << PTRACE_CFI_LP_EN_BIT)
+#define PTRACE_CFI_LP_LOCK_STATE (1 << PTRACE_CFI_LP_LOCK_BIT)
+#define PTRACE_CFI_ELP_STATE (1 << PTRACE_CFI_ELP_BIT)
+#define PTRACE_CFI_SS_EN_STATE (1 << PTRACE_CFI_SS_EN_BIT)
+#define PTRACE_CFI_SS_LOCK_STATE (1 << PTRACE_CFI_SS_LOCK_BIT)
+#define PTRACE_CFI_SS_PTR_STATE (1 << PTRACE_CFI_SS_PTR_BIT)
+
+#define PRACE_CFI_STATE_INVALID_MASK ~(PTRACE_CFI_LP_EN_STATE | \
+ PTRACE_CFI_LP_LOCK_STATE | \
+ PTRACE_CFI_ELP_STATE | \
+ PTRACE_CFI_SS_EN_STATE | \
+ PTRACE_CFI_SS_LOCK_STATE | \
+ PTRACE_CFI_SS_PTR_STATE)
+
+struct __cfi_status {
+ __u64 cfi_state;
+};
+
+struct user_cfi_state {
+ struct __cfi_status cfi_status;
+ __u64 shstk_ptr;
+};
+
#endif /* __ASSEMBLY__ */
#endif /* _UAPI_ASM_RISCV_PTRACE_H */
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index ea67e9fb7a58..933a3d26d33c 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -19,6 +19,7 @@
#include <linux/regset.h>
#include <linux/sched.h>
#include <linux/sched/task_stack.h>
+#include <asm/usercfi.h>
enum riscv_regset {
REGSET_X,
@@ -31,6 +32,9 @@ enum riscv_regset {
#ifdef CONFIG_RISCV_ISA_SUPM
REGSET_TAGGED_ADDR_CTRL,
#endif
+#ifdef CONFIG_RISCV_USER_CFI
+ REGSET_CFI,
+#endif
};
static int riscv_gpr_get(struct task_struct *target,
@@ -184,6 +188,87 @@ static int tagged_addr_ctrl_set(struct task_struct *target,
}
#endif
+#ifdef CONFIG_RISCV_USER_CFI
+static int riscv_cfi_get(struct task_struct *target,
+ const struct user_regset *regset,
+ struct membuf to)
+{
+ struct user_cfi_state user_cfi;
+ struct pt_regs *regs;
+
+ memset(&user_cfi, 0, sizeof(user_cfi));
+ regs = task_pt_regs(target);
+
+ if (is_indir_lp_enabled(target)) {
+ user_cfi.cfi_status.cfi_state |= PTRACE_CFI_LP_EN_STATE;
+ user_cfi.cfi_status.cfi_state |= is_indir_lp_locked(target) ?
+ PTRACE_CFI_LP_LOCK_STATE : 0;
+ user_cfi.cfi_status.cfi_state |= (regs->status & SR_ELP) ?
+ PTRACE_CFI_ELP_STATE : 0;
+ }
+
+ if (is_shstk_enabled(target)) {
+ user_cfi.cfi_status.cfi_state |= (PTRACE_CFI_SS_EN_STATE |
+ PTRACE_CFI_SS_PTR_STATE);
+ user_cfi.cfi_status.cfi_state |= is_shstk_locked(target) ?
+ PTRACE_CFI_SS_LOCK_STATE : 0;
+ user_cfi.shstk_ptr = get_active_shstk(target);
+ }
+
+ return membuf_write(&to, &user_cfi, sizeof(user_cfi));
+}
+
+/*
+ * Does it make sense to allowing enable / disable of cfi via ptrace?
+ * Not allowing enable / disable / locking control via ptrace for now.
+ * Setting shadow stack pointer is allowed. GDB might use it to unwind or
+ * some other fixup. Similarly gdb might want to suppress elp and may want
+ * to reset elp state.
+ */
+static int riscv_cfi_set(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user *ubuf)
+{
+ int ret;
+ struct user_cfi_state user_cfi;
+ struct pt_regs *regs;
+
+ regs = task_pt_regs(target);
+
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_cfi, 0, -1);
+ if (ret)
+ return ret;
+
+ /*
+ * Not allowing enabling or locking shadow stack or landing pad
+ * There is no disabling of shadow stack or landing pad via ptrace
+ * rsvd field should be set to zero so that if those fields are needed in future
+ */
+ if ((user_cfi.cfi_status.cfi_state &
+ (PTRACE_CFI_LP_EN_STATE | PTRACE_CFI_LP_LOCK_STATE |
+ PTRACE_CFI_SS_EN_STATE | PTRACE_CFI_SS_LOCK_STATE)) ||
+ (user_cfi.cfi_status.cfi_state & PRACE_CFI_STATE_INVALID_MASK))
+ return -EINVAL;
+
+ /* If lpad is enabled on target and ptrace requests to set / clear elp, do that */
+ if (is_indir_lp_enabled(target)) {
+ if (user_cfi.cfi_status.cfi_state &
+ PTRACE_CFI_ELP_STATE) /* set elp state */
+ regs->status |= SR_ELP;
+ else
+ regs->status &= ~SR_ELP; /* clear elp state */
+ }
+
+ /* If shadow stack enabled on target, set new shadow stack pointer */
+ if (is_shstk_enabled(target) &&
+ (user_cfi.cfi_status.cfi_state & PTRACE_CFI_SS_PTR_STATE))
+ set_active_shstk(target, user_cfi.shstk_ptr);
+
+ return 0;
+}
+#endif
+
static const struct user_regset riscv_user_regset[] = {
[REGSET_X] = {
.core_note_type = NT_PRSTATUS,
@@ -224,6 +309,16 @@ static const struct user_regset riscv_user_regset[] = {
.set = tagged_addr_ctrl_set,
},
#endif
+#ifdef CONFIG_RISCV_USER_CFI
+ [REGSET_CFI] = {
+ .core_note_type = NT_RISCV_USER_CFI,
+ .align = sizeof(__u64),
+ .n = sizeof(struct user_cfi_state) / sizeof(__u64),
+ .size = sizeof(__u64),
+ .regset_get = riscv_cfi_get,
+ .set = riscv_cfi_set,
+ },
+#endif
};
static const struct user_regset_view riscv_user_native_view = {
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index 819ded2d39de..ee30dcd80901 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -545,6 +545,8 @@ typedef struct elf64_shdr {
#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
#define NN_RISCV_TAGGED_ADDR_CTRL "LINUX"
#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */
+#define NN_RISCV_USER_CFI "LINUX"
+#define NT_RISCV_USER_CFI 0x903 /* RISC-V shadow stack state */
#define NN_LOONGARCH_CPUCFG "LINUX"
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
#define NN_LOONGARCH_CSR "LINUX"
--
2.43.0
next prev parent reply other threads:[~2025-07-11 19:47 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-11 19:46 [PATCH v18 00/27] riscv control-flow integrity for usermode Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 01/27] mm: VM_SHADOW_STACK definition for riscv Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 02/27] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 03/27] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 04/27] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 05/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 06/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 07/27] riscv/mm: manufacture shadow stack pte Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 08/27] riscv/mm: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 09/27] riscv/mm: write protect and shadow stack Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 10/27] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 11/27] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 12/27] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 13/27] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 14/27] riscv: Implements arch agnostic indirect branch tracking prctls Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 15/27] riscv/traps: Introduce software check exception and uprobe handling Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 16/27] riscv: signal: abstract header saving for setup_sigcontext Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 17/27] riscv/signal: save and restore of shadow stack for signal Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 18/27] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2025-07-11 19:46 ` Deepak Gupta [this message]
2025-07-11 19:46 ` [PATCH v18 20/27] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 21/27] riscv: kernel command line option to opt out of user cfi Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 22/27] riscv: enable kernel access to shadow stack memory via FWFT sbi call Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 23/27] arch/riscv: compile vdso with landing pad and shadow stack note Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 24/27] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 25/27] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 26/27] riscv: Documentation for shadow stack on riscv Deepak Gupta
2025-07-11 19:46 ` [PATCH v18 27/27] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
2025-07-11 20:25 ` [PATCH v18 00/27] riscv control-flow integrity for usermode Deepak Gupta
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