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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?gwjJYoM1PkJ0abFlcvKtzOzSjgibJsMvYuMQU1zkg3XoJaSgQNGj4b9+JKs5?= =?us-ascii?Q?jeGP7+O8stFy2GS84BJ5TIbO7Z/gjI1VjvKb9oskl/zaqxZXhXkDO23zE7I1?= =?us-ascii?Q?dZ5NwtejbwLSSZD/B79ZZpEiPGJ3a5p+VbNa3jpq1qKpls0y43eES7c0E4Lw?= =?us-ascii?Q?V2STFcN8PFPAQT+vWPLLJbYGLdKBVZi9jY6sJF6MUfwUNiza4orBZ9qBBCSf?= =?us-ascii?Q?RjS5gE+r0s5kz169fIBZDo5FCsxiAiO8gaY1fNIABuG9kAooFHoiWnQrtARu?= =?us-ascii?Q?ckw0HHaFchdeiUzbdUN6W49uCi6VOKorO/MEYScRRLZe8zLTGAh1awkaEAUw?= =?us-ascii?Q?9KWJmcfIKplZV1qVnx51gDN6kuqA7+YDaaTlu6Hjdtqqmn5IN60dsfTtpsK8?= =?us-ascii?Q?t8T3O+ipVAmOc1pXKnojJrDusrhdlrwMThgzJ/akcjvVlMsAsbTeP7gfwHz/?= =?us-ascii?Q?+eTXHVuIuL3wtkARZjK/+5UaLIWpQ7+PVtyw9vSW3Ga9kA9WavJ/zeESix8w?= =?us-ascii?Q?5C3gO1/3xeSSDycOau5Qd18A3TPTuKctvrsYNHmUBAqrzkszxyu5k7q5x9oN?= =?us-ascii?Q?MXRTccd5nTNfaHR3n7aZ3k2O8r1tnSpGeffrwbO+1mZ9L5oVVQrfoe2f40xk?= =?us-ascii?Q?NMVYjzmJrxNVTITnewJBOK63tQI/sBBf6WM8+714y7m4UBr7GCCbBd9oIDq8?= =?us-ascii?Q?6E2US8YH1Re7gukYK8+9N9sQRhubu+TRR7lXxaQ6uAeEnhlCqTQZBAOvZFIT?= =?us-ascii?Q?K8sd0aNoMIgxSVWuBoVSnFFZSTF9hPlLRBJxCecXn2kjIAOIxHtql/eO4fyr?= =?us-ascii?Q?ljyai1KO1qbUJixpZRHkUZSxHhQSXrMjTniEoe0eNGDiV8G6qX8eNu4pdwQU?= =?us-ascii?Q?1025+wNi5WAkFwr8BYofrH/2+y6Vfx087H1sIRS/xfOiYMN0dtHURfazalmr?= =?us-ascii?Q?xhSNm1K7UOZp23ScA/78qoycUB3TFAaZPWpz7Lv2iyDYVtO8wDd5qKxdPTiq?= =?us-ascii?Q?IpSwRcZ93ZTwqFfON07sweocYZ5E/AEQa8Y7XlYqH6fgHtWfcBJnaed9SMty?= =?us-ascii?Q?TqSNzo6uNregMWO5Yu04TNt7V9e0+t8DYJ40oeBntdaCxQCd2od/dFOKZ+RM?= =?us-ascii?Q?FPTIbr7j03tQBTPQ5aUhMhMs2ubWjHdZNzITKmPuoitmjp08ZLnbKPZkQ32u?= =?us-ascii?Q?MyjveA+493yel7+sLlU6n43CjyRK5LJrvf9HBH4c3w/SoR4QsQ22en1O/3Bz?= =?us-ascii?Q?ixq6QexicBjIQ52BaKPTNzoQ6LxiiT0DjEr6hUTeizUVM8OQAtxqol7/DZzK?= =?us-ascii?Q?JOJfduSH1Uqlnj+4YpQj23THZjSObvWTeJYogdjfALsWL/DHYiZB2loqhPCr?= =?us-ascii?Q?T/oHLRyYPJV7PxSxY1jrXXRzeIWXIvZuadP5Rv1QIsf3IoeBfJXduMgFItzN?= =?us-ascii?Q?hFORVo1JCqDBCmNIZW+jtPWIKiuWt9JlF4X8vSYi2+2Jr+YCJ4AkQ1yMn3Jt?= =?us-ascii?Q?CC8cxyFGxhlv8shGgbEFCWG6WTcl6qw+C80/boVRLvjvawLhWZBJ4cimT7gV?= =?us-ascii?Q?ekstVn7WnTzJkDbTn2Mo/Zf67Vgcg1GDaM/kHJDv?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d0bf4f4-05a0-418d-307c-08ddf09c9e37 X-MS-Exchange-CrossTenant-AuthSource: SN7PR12MB8059.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2025 19:02:41.8632 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MZbigEarG2NdnXiDxH/DGEYfCAwGWTIpt+R8tAuGc2ShUDk2+7POM4vXm+GQPZB13rlN9NhbaZ9+l3Hw+BzEVQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9166 On Wed, Sep 10, 2025 at 02:09:55PM -0400, Joel Fernandes wrote: [...] > > > + /// Allocate IRQ vectors for this PCI device. > > > + /// > > > + /// Allocates between `min_vecs` and `max_vecs` interrupt vectors for the device. > > > + /// The allocation will use MSI-X, MSI, or legacy interrupts based on the `irq_types` > > > + /// parameter and hardware capabilities. When multiple types are specified, the kernel > > > + /// will try them in order of preference: MSI-X first, then MSI, then legacy interrupts. > > > + /// This is called during driver probe. > > > + /// > > > + /// # Arguments > > > + /// > > > + /// * `min_vecs` - Minimum number of vectors required > > > + /// * `max_vecs` - Maximum number of vectors to allocate > > > + /// * `irq_types` - Types of interrupts that can be used > > > + /// > > > + /// # Returns > > > + /// > > > + /// Returns the number of vectors successfully allocated, or an error if the allocation > > > + /// fails or cannot meet the minimum requirement. > > > + /// > > > + /// # Examples > > > + /// > > > + /// ``` > > > + /// // Allocate using any available interrupt type in the order mentioned above. > > > + /// let nvecs = dev.alloc_irq_vectors(1, 32, IrqTypes::all())?; > > > + /// > > > + /// // Allocate MSI or MSI-X only (no legacy interrupts) > > > + /// let msi_only = IrqTypes::default() > > > + /// .with(IrqType::Msi) > > > + /// .with(IrqType::MsiX); > > > + /// let nvecs = dev.alloc_irq_vectors(4, 16, msi_only)?; > > > + /// ``` > > > + pub fn alloc_irq_vectors( > > > + &self, > > > + min_vecs: u32, > > > + max_vecs: u32, > > > + irq_types: IrqTypes, > > > + ) -> Result { > > > + // SAFETY: `self.as_raw` is guaranteed to be a pointer to a valid `struct pci_dev`. > > > + // `pci_alloc_irq_vectors` internally validates all parameters and returns error codes. > > > + let ret = unsafe { > > > + bindings::pci_alloc_irq_vectors(self.as_raw(), min_vecs, max_vecs, irq_types.raw()) > > > + }; > > > + > > > + to_result(ret)?; > > > + Ok(ret as u32) > > > + } > > > > This is only valid to be called from the Core context, as it modifies internal > > fields of the inner struct device. > > It is called from core context, the diff format confuses. > > > > Also, it would be nice if it would return a new type that can serve as argument > > for irq_vector(), such that we don't have to rely on random integers. > > Makes sense, I will do that. > By the way, the "ret" value returned by pci_alloc_irq_vectors() is the number of vectors, not the vector index. So basically there are 3 numbers that mean different things: 1. Number of vectors (as returned by alloc_irq_vectors). 2. Index of a vector (passed to pci_irq_vector). 3. The Linux IRQ number (passed to request_irq). And your point is well taken, in fact even in current code there is ambiguity: irq_vector() accepts a vector index, where as request_irq() accepts a Linux IRQ number, which are different numbers. I can try to clean that up as well but let me know if you had any other thoughts. In fact, I think Device::request_irq() pci should just accept IrqRequest? thanks, - Joel