Re: [PATCH v4 1/6] nova-core: bitfield: Move bitfield-specific code from register! into new macro

[Greg KH <gregkh@linuxfoundation.org>]

On Sat, Sep 20, 2025 at 02:22:27PM -0400, Joel Fernandes wrote:
> The bitfield-specific into new macro. This will be used to define
> structs with bitfields, similar to C language.
> 
> Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev>
> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
> ---
>  drivers/gpu/nova-core/bitfield.rs    | 314 +++++++++++++++++++++++++++
>  drivers/gpu/nova-core/nova_core.rs   |   3 +
>  drivers/gpu/nova-core/regs/macros.rs | 259 +---------------------
>  3 files changed, 327 insertions(+), 249 deletions(-)
>  create mode 100644 drivers/gpu/nova-core/bitfield.rs
> 
> diff --git a/drivers/gpu/nova-core/bitfield.rs b/drivers/gpu/nova-core/bitfield.rs
> new file mode 100644
> index 000000000000..ba6b7caa05d9
> --- /dev/null
> +++ b/drivers/gpu/nova-core/bitfield.rs
> @@ -0,0 +1,314 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +//! Bitfield library for Rust structures
> +//!
> +//! Support for defining bitfields in Rust structures. Also used by the [`register!`] macro.
> +//!
> +//! # Syntax
> +//!
> +//! ```rust
> +//! #[derive(Debug, Clone, Copy)]
> +//! enum Mode {
> +//!     Low = 0,
> +//!     High = 1,
> +//!     Auto = 2,
> +//! }
> +//!
> +//! impl TryFrom<u8> for Mode {
> +//!     type Error = u8;
> +//!     fn try_from(value: u8) -> Result<Self, Self::Error> {
> +//!         match value {
> +//!             0 => Ok(Mode::Low),
> +//!             1 => Ok(Mode::High),
> +//!             2 => Ok(Mode::Auto),
> +//!             _ => Err(value),
> +//!         }
> +//!     }
> +//! }
> +//!
> +//! impl From<Mode> for u32 {
> +//!     fn from(mode: Mode) -> u32 {
> +//!         mode as u32
> +//!     }
> +//! }
> +//!
> +//! #[derive(Debug, Clone, Copy)]
> +//! enum State {
> +//!     Inactive = 0,
> +//!     Active = 1,
> +//! }
> +//!
> +//! impl From<bool> for State {
> +//!     fn from(value: bool) -> Self {
> +//!         if value { State::Active } else { State::Inactive }
> +//!     }
> +//! }
> +//!
> +//! impl From<State> for u32 {
> +//!     fn from(state: State) -> u32 {
> +//!         state as u32
> +//!     }
> +//! }
> +//!
> +//! bitfield! {
> +//!     struct ControlReg {
> +//!         3:0       mode        as u8 ?=> Mode;
> +//!         7         state       as bool => State;
> +//!     }
> +//! }

As discussed at the conference this week, I do object to this as it
will allow the same mistakes to happen that we used to do in the kernel
for a long time before the regmap() api happened, along with GENMASK().

The issue is that you are going to want to take these bitfields as part
of a larger structure, and attempt to "lay it over" a chunk of memory
that came from, or is going to, hardware.  When that happens, all of the
endian issues of mis-matches between hardware and cpus come into play,
which is not able to be properly expressed here at all, unless you
attempt to either resolve it all later on in something like the regmap
api, or you have #ifdef stuff to attempt to capture all of the possible
combinations and deal with it at build time (which is strongly never
recommended, but is what we used to do in previous decades.)

Your example code using this is nice, and it shows how to set up, and
query these bits, but that's not anything anyone actually does in the
kernel, what they want to do is read/write from hardware with this.

So, how does that work?  Where does this "drop down" to the native
bus/memory transactions and swizzle the bits properly to work correctly?

And where does this allow us to define things like BIT(2) for values?
(ok, that's kind of not the point of this patch series, but it will come
up over time...)

Ideally, this would map to our existing regmap api, which does handle
all of this properly, but I know that's not usually used by PCI drivers
like where this code is coming from, as they "just assume" endian
formats are all little and can get away with it due to the limited
nature of different hardware types for their hardware.

Also, a larger meta-comment, why doesn't rust have bit types?  Why does
everyone either have to roll their own or rely on an external crate?  Is
anyone working to provide native bit support to the language?  I'm sure
the embedded people would love it as I imagine it's what they reach for
first when using the language on their hardware.

thanks,

greg k-h