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Fri, 10 Oct 2025 01:03:38 -0700 From: Zhi Wang To: CC: , , , , , , , , , , , , , , , , , , , , , Subject: [RFC 0/6] rust: pci: add config space read/write support Date: Fri, 10 Oct 2025 08:03:24 +0000 Message-ID: <20251010080330.183559-1-zhiw@nvidia.com> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D8:EE_|CY5PR12MB9055:EE_ X-MS-Office365-Filtering-Correlation-Id: e6d6eeb2-9056-4093-69b4-08de07d38bce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/Ub1vorti1Xx8XH7ypDriTxaGwkFYIzkkcf+RNPFRs0cpnL3AKSO+IwA2aYp?= =?us-ascii?Q?92CAd/5y/ixyDIzTo2Q1HzsU15wXYDw/b7/FcDaKC3Mg4+6Qq7xyDajtu8DA?= =?us-ascii?Q?fJiCZAqe7aZD9R8PZXpx6fiLNdfKpJaaFJkwtPQ3uRzPwsd5onXgdhTYyHGh?= =?us-ascii?Q?zvMxnBLtV3nbgwg/cdJyxw1jttBHX4u1u//dIsb3xOnuJx4BscSUo6clI1i9?= =?us-ascii?Q?pFVB23nb9xUbcGvNS3j3AfftQrg4mwKiGlzrglL90N3Mx+kaAFV1SgeG+Liu?= =?us-ascii?Q?Kpu1Dj8ZQzNSt5+rafgGtSZLicrhtqPmN6UUcABgXHP2CP7m48nXUfHeqljB?= =?us-ascii?Q?dGpKlbHzQQveAW1kd4CDvO4sCF5kCUM2VohCqYwJfAy69OVd4jsDd7Pzh6f+?= =?us-ascii?Q?6ufsLbiWc328pac0rhgAKfRzGQxKPL9KahD4xvIKOyH7TcyvDbUc9sKLeQ7S?= =?us-ascii?Q?VOPF+1qtbl8PGbiat8tgcWviSqOHONm4MeOxHq9zYlG3VAldzirR2TC0E2wF?= =?us-ascii?Q?JRZS4hdfbdi/0S3qE1KbcVHNWSP1kha6PIpqfuGbIQe+X2dzQDFK422w61mu?= =?us-ascii?Q?r+bP+ZGaIiNP3I9MMAPIqQKA61LMKdNcXMmv2TMqDHeX66M1yJlxRoaieT7z?= =?us-ascii?Q?g2habONLa7D5VVYKPt995ehbTz3exIkWbKXJw/7Dy75no4IoFYoArvCMbMRq?= =?us-ascii?Q?KBpveFVmiyVDFLwUDRNYtxbCRlrCyVVxUjQYm6YipVmIBn/f/NGfRq3Em236?= =?us-ascii?Q?pTc9wYZ+fsKria9ZOgfiYYqyokOfhhRGczpsLFN9HgYjB+4QOuDv+uZfJ8Sb?= =?us-ascii?Q?rjmuEsdijzCEuxNu9KJCn6HesZl5iJ7Hu1Eq8/x8yR0xPFZkRhNz0JJe/Vh0?= =?us-ascii?Q?lrI2DPwU+0dhNt4gn9RQuPXwPolwLsyd+4LMRh2AZpvEOQMD7B9SNr8E42bz?= =?us-ascii?Q?UFsgAeHG6f/l8+63AvNRayTrLC50ZKK78v4T24i8gBhTHfcX9ltjQe6WyZr0?= =?us-ascii?Q?uM/MtPPqCclHCdJLdJdyjEo4O2ycBabTGQ4BRpf00racIB97oVjmAj8pQ8rG?= =?us-ascii?Q?ts83BGfh++ohb1f207+DQNH4HCWWhCO5I1eFbOJ9e1Q944IAayvNaKIRLEzp?= =?us-ascii?Q?Q86gix9WLjWnK7P+rG1ic5Gega5dCITc0gSpToPwSBslX/aJRfan5fbg6tOh?= =?us-ascii?Q?2wi7n12enSEOlZaGSIkYu/6djVsUUPL2jyeCkOYrbbzW4R6FTXGv1ubi+WVq?= =?us-ascii?Q?HnKtjFx878Z+rIyns/Y1qikHMnOoqhTXvZaLe1sf4cxUPO9zlJ6/1sgelDwk?= =?us-ascii?Q?qb6t581j2QbftjTe1leFExUbUiWk4mvJkxg8zpaE7mlbDSbQJA4uiKbkI5um?= =?us-ascii?Q?wtm8M4MTTXhaN4i8yIk5txahmvPFvc9zEGBx91E4Y1XDLEhTNRQyYnFWFr2J?= =?us-ascii?Q?IL+G+k9O8JoLqdvZH8LXsyhFUbukiWGeDyzpwKi4TYc/hEWRTrLJRgIwpB1u?= =?us-ascii?Q?r8TFHVmHLHxSKRjZKNj8/PdMYLi8ArMZhpyqWhBRaJpc2n94LigY2TO0EA?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 08:03:49.6621 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6d6eeb2-9056-4093-69b4-08de07d38bce X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB9055 In the NVIDIA vGPU RFC [1], the PCI configuration space access is required in nova-core for preparing gspVFInfo when vGPU support is enabled. This series is the following up of the discussion with Danilo for how to introduce support of PCI configuration space access in Rust PCI abstrations. Bascially, we are thinking of introducing another backend for PCI configuration space access similar with Kernel::Io. This ideas of this series are: - Factor out a common trait IoRegion for other accessors to share the same compiling/runtime check like before. - Factor the MMIO read/write macros from the define_read! and define_write! macros. Thus, define_{read, write}! can be used in other backend. In detail: * Introduce `call_mmio_read!` and `call_mmio_write!` helper macros to encapsulate the unsafe FFI calls. * Update `define_read!` and `define_write!` macros to delegate to the call macros. * Export `define_read` and `define_write` so they can be reused for other I/O backends (e.g. PCI config space). - Add a helper to query configuration space size. This is mostly for runtime check. - Implement the PCI configuration space access backend in PCI Abstractions. In detail: * `struct ConfigSpace` wrapping a `pdev: ARef`. * `IoRegion` implementation returning the device's `cfg_size`. * `call_config_read!` and `call_config_write!` macros bridging to the existing C helpers (`pci_read_config_*` / `pci_write_config_*`). * Read accessors: `read8/16/32` and `try_read8/16/32`. * Write accessors: `write8/16/32` and `try_write8/16/32`. - Introduce an rust wrapper for pci_find_ext_capability(). Thus, the rust driver can locate the extended PCI configuration caps. Open: The current kernel::Io MMIO read/write doesn't return a failure, because {read, write}{b, w, l}() are always successful. This is not true in pci_{read, write}_config{byte, word, dword}() because a PCI device can be disconnected from the bus. Thus a failure is returned. - Do we still need a non-fallible version of read/write for config space? A rust panic in accessing the PCI config space when device is unexpectedly disconnected seems overkill. Zhi Wang (6): rust: io: refactor Io helpers into IoRegion trait rust: io: factor out MMIO read/write macros rust: pci: add a helper to query configuration space size rust: pci: add config space read/write support rust: pci: add helper to find extended capability [!UPSTREAM] nova-core: test configuration routine. drivers/gpu/nova-core/driver.rs | 4 + rust/kernel/io.rs | 132 +++++++++++++++++++++----------- rust/kernel/pci.rs | 74 ++++++++++++++++++ 3 files changed, 164 insertions(+), 46 deletions(-) -- 2.47.3