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Thu, 16 Oct 2025 14:02:57 -0700 From: Zhi Wang To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 0/5] rust: pci: add config space read/write support, take 1 Date: Thu, 16 Oct 2025 21:02:45 +0000 Message-ID: <20251016210250.15932-1-zhiw@nvidia.com> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AC:EE_|CY1PR12MB9652:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e995f19-8d08-4e53-f724-08de0cf77756 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+JNsB8vDlZfojxKrKMh9mRI/vRncTCdwOdD+dmY1mDoIcIb5okeUKR/CXcIH?= =?us-ascii?Q?VrLGIwjGHllHjbwf1qmfa5RH5hJDFhNQa8d9ouxzEw/NpkiCXvEFALZ1mvzP?= =?us-ascii?Q?qVLq16gd4Lo2CzTM/mJ91lVtlBIMDEwUXeCRabjM3iTEW5XP4tORFPicl4p/?= =?us-ascii?Q?RBqEgnD9/rjkwBgUdKcUkUTYfd2OlV6tl+CjB2y83Haft+FznLq3YECrEQcV?= =?us-ascii?Q?Ews4kPMCwjCsPaHlWiRrQrLZWYQP3JwoeFIHPvou83oU7+zcbhmV5rVyshx/?= =?us-ascii?Q?LVc9fjrkzBIzzy13EJj/MgJcWJdPZ0SS+8qnk3D46UmAKo/ki4BcJDmeZnh/?= =?us-ascii?Q?OQNdOQWhEZMXr1W18H/N5UL3Lxlgwa78D0N81tPqdCFLT+PkyHbFycreum0F?= =?us-ascii?Q?rtQg/DnYkTrJfX1drG61oDIKtBzXauSA9J57oI5u6EYcTW/T3uj5IaD2RdG0?= =?us-ascii?Q?u4iCdcWt6QMStUtrx7AsTmvC51B1ioy2OE6Q5lubd36g/MdPn5wtC2OfxHiY?= =?us-ascii?Q?Kuw1jBiPkLJo/KtcHP7RYkrAaSA714OH4UlyGaZsEkM562sWnIqVv7tI5rAU?= =?us-ascii?Q?rMScn+jmdZJ1bAygJuDxIYkvhnZe2wo2121t5eR3eTMgkwQfntih4WUJNWqq?= =?us-ascii?Q?b8fU+Dj8DzmNbtA5CtDCcwYVkER2rramJryoIqAR3iZeMhPNdukQvnCl8U1W?= =?us-ascii?Q?KQpRuwQBaho2DEPdu6CicnU3RpwHyWvtQhyAMEm/kklQPtMx7C+kMPKAOTXF?= =?us-ascii?Q?OTj66q/37LSwmFsM/tQstSumcw8O/8OiVtQfDFaVEOZmMvkb9oavUmviVMZN?= =?us-ascii?Q?wQrZLMCsRYW96pvSVpNmXNtksUnproDZDHa+Z4WMwMCTVP9oXpusN5OawFAz?= =?us-ascii?Q?MnHL9azjIBVfSY2xewxd2wrBXkjz3S1Hg8HSCqS7ezIFV49pWo5NkbyVOyo6?= =?us-ascii?Q?/FvhptUy4yaQwx7TH/xXz/BOIxzmT/WQcYWne+xpehHzzbcENs3F5qiDBqNs?= =?us-ascii?Q?vLF40fmSd7DIXDVA6sIp7/xqzrXgWszkjHJB4zNVkumibZfVWQj9onntDjYF?= =?us-ascii?Q?acKHWptpZlpPg1wvFdmbI1jkwcBPdYZWinBSdaXV6R79I6QXLDvDdoXp19Lv?= =?us-ascii?Q?LPJUdqDBgBlpNW42IA6CkKi9zOAqo6a3IiV/FotW+n5Rab3DR06CbTYVUH5v?= =?us-ascii?Q?PpR7Aw1nsqCeSztsxhYk6Yih4uixOSvyGVQAyztyEvE9+vetBkZ6M7wPFXU1?= =?us-ascii?Q?QeyeargSciYQ3AbRJzErWI2OcdCRFrz5vodM4dpAZyxWqnovcb3c/1QpiDMJ?= =?us-ascii?Q?S0pislHk9PJNNruIUyITH8cvfNLaRW56UHKDQvZEaokHKvdIMojNPJtWf+wi?= =?us-ascii?Q?CF6s9Lm2dSslu6QrzoUWRf/AirXvdVm2pmOsI3Us3Y7RtJw7xVvX62Ut8sda?= =?us-ascii?Q?Xnus7trVRNdVn3DkkNnmURqGKAjiFSAaP1eXReU7ExB0NgNdFNLNvrYeyqo0?= =?us-ascii?Q?RUHqLWDcLluEZbnpOBkCrnTSu1PWmmOKmtmLl3lLAG90iLUSLosX/wM2v0V4?= =?us-ascii?Q?XDeVmunxpAd7sqrcusw=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2025 21:03:33.0838 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e995f19-8d08-4e53-f724-08de0cf77756 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9652 In the NVIDIA vGPU RFC [1], the PCI configuration space access is required in nova-core for preparing gspVFInfo when vGPU support is enabled. This series is the following up of the discussion with Danilo for how to introduce support of PCI configuration space access in Rust PCI abstrations. Bascially, we are thinking of introducing another backend for PCI configuration space access similar with Kernel::Io. This ideas of this series are: - Factor out a common trait 'Io' for other accessors to share the same compiling/runtime check like before. - Factor the MMIO read/write macros from the define_read! and define_write! macros. Thus, define_{read, write}! can be used in other backend. - Add a helper to query configuration space size. This is mostly for runtime check. - Implement the PCI configuration space access backend in PCI abstractions. v2: - Factor out common trait as 'Io' and keep the rest routines in original 'Io' as 'Mmio'. (Danilo) - Rename 'IoRaw' to 'MmioRaw'. Update the bus MMIO implemention to use 'MmioRaw'. - Intorduce pci::Device::config_space(). (Danilo) - Implement both infallible and fallible read/write routines, the device driver devicdes which version should be used. Moving forward: - Define and use register! macros. - Introduce { cap, ecap } search and read. RFC v1: https://lore.kernel.org/all/20251010080330.183559-1-zhiw@nvidia.com/ [1] https://lore.kernel.org/all/20250903221111.3866249-1-zhiw@nvidia.com/ Zhi Wang (5): rust/io: factor common I/O helpers into Io trait and specialize Mmio rust: io: factor out MMIO read/write macros rust: pci: add a helper to query configuration space size rust: pci: add config space read/write support nova-core: test configuration routine. drivers/gpu/nova-core/driver.rs | 4 + drivers/gpu/nova-core/regs/macros.rs | 36 +++--- rust/kernel/io.rs | 161 +++++++++++++++++---------- rust/kernel/io/mem.rs | 16 +-- rust/kernel/pci.rs | 79 ++++++++++++- 5 files changed, 206 insertions(+), 90 deletions(-) -- 2.47.3