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Wysocki" , Viresh Kumar , Sebastian Andrzej Siewior , Ingo Molnar , Ryo Takakura , K Prateek Nayak , "open list:CPU FREQUENCY SCALING FRAMEWORK" Subject: Re: [PATCH v13 01/17] preempt: Track NMI nesting to separate per-CPU counter Message-ID: <20251020204421.GA197647@joelbox2> References: <20251013155205.2004838-1-lyude@redhat.com> <20251013155205.2004838-2-lyude@redhat.com> <20251014104839.GN4067720@noisy.programming.kicks-ass.net> <4a237ec0-05ae-439b-a1cb-6b7f451c0d7e@nvidia.com> <20251014194349.GC1206438@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251014194349.GC1206438@noisy.programming.kicks-ass.net> X-ClientProxiedBy: BL1PR13CA0108.namprd13.prod.outlook.com (2603:10b6:208:2b9::23) To SN7PR12MB8059.namprd12.prod.outlook.com (2603:10b6:806:32b::7) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN7PR12MB8059:EE_|SN7PR12MB6671:EE_ X-MS-Office365-Filtering-Correlation-Id: 7cd026b1-0be7-42e6-fdcc-08de101972f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Ak0Hv85X/N5sN0qdf+lc2yw4C5wJd+GnPfYAusi5mm6zJtM1pRMoNNR44iC/?= =?us-ascii?Q?YZZ7iPdoMbJl3myqzcuIiIzBcJi4SrCU8E5yMNO/G+LmPLmsv+9qCxDNn+68?= =?us-ascii?Q?TaGYUOVAU2re5WB81n7KsXspE93lelowylvvTKfjJv4P5sbvHLemu2lGV9rP?= =?us-ascii?Q?Qje80HHxV4k3mY3PDKu2ml0Ff2i7NUESJHrYvqVsWFZLQKUZtduwY8+/acgp?= =?us-ascii?Q?MqTrNs8753bn+kxMuz72qILnlU5nPce3J66clsK0fHbpcGbfrlD2hfHR+sqr?= =?us-ascii?Q?M9ybCiPkScea+YR3izXDbFKFGGLnuhfyU3gJjfOldi07Xo8xS5rcu670VCcE?= =?us-ascii?Q?NL1sC8TsvRoflFzNPVvOmxWqCEanFkG8EWkHtynzG0BVxLBghvPNRuf3UUXK?= =?us-ascii?Q?2M8djSvkjQlYUVo3hTD8XP4qUIbKVLZZyTY9SEAmZx98Z3LNHlgPiz/etica?= =?us-ascii?Q?ZOvW7ok8wURdzJC0pnxaza9S2nGBmzOfrRGKvP/ZjpQ/5MOH/ms/JceO+ZnT?= =?us-ascii?Q?zgk8qGd8FSVeQr2IBoxGunQma1U3LxupT+c5lJsWChZQJPSUAdP8ug4kDFK1?= =?us-ascii?Q?9zNb2ZFpIUTQ2ImCpA8778mzW2k91wdTd1lE5cWxwDnUqOWY4vkxVDPDSlur?= =?us-ascii?Q?PyrgbcokJRELMgAfftnB9dW1dybzBYQkhq53/tpJgoYxsHXIrN34HrOKS94P?= =?us-ascii?Q?ylN0UMuiPexkn9jgHracU/nWpZ12NucZnANeXlU7H4ekjkJ5GCR3tvp9GgO0?= =?us-ascii?Q?8sItyzpXGoP0gz3Rzq/mZIh0JXJfZ9JB9ErVV2n7IvGhG6bMdu6JLFhBftq4?= =?us-ascii?Q?OSkFXkzHIrxlAI8m8budkWyb/a12P351Cnzj9qVVmav+K5JYkc85YTSsNsgS?= =?us-ascii?Q?HKSY1x5vmAZX6SPf6tNrFqbS3FGERZe22687KcpSin0Aq15R3iMWsA3ZIt9Y?= =?us-ascii?Q?voAWmOThmuQRWwL2o/v3/go1eicxozUh38I8+HHD45MTHc7DQVDg/fPSk9C9?= =?us-ascii?Q?+vg/Xfu70O3+1l+vGDNd+iAgrNDaucgNbPIo6p7G1gzHnFquaLeBPC/mo3US?= =?us-ascii?Q?9khP6WQO7XQ8rawmUIFIRHT0cnI27QjVw9dOprNWv/0BKRdaq3uErhmv3yzg?= =?us-ascii?Q?0Wei4YF6DGMrGflOY3Pl2aE4r7KCreEWgnIYMAl88S1oKw8P22L/619kv2bZ?= =?us-ascii?Q?Bs6jPjyuTt8Yo4f0RjzMkzhesk6ZjN3GMB6GnA3rE9qwOKPhareca8vxfjka?= =?us-ascii?Q?CQ5V/KQepHicv0BUK3EnHdL23hGhkn5+os9WAOVX7Y/IxLyXfJyWQmizaE1i?= =?us-ascii?Q?/TTUsuFICHIJ+uFmjYyvonNoqnnqXpsKcGYQbSxbeILUdU4h+mkmxe7OrmSt?= =?us-ascii?Q?29b52CFcQn0wspINnfTdz1oji8jE1yjYGRZfyOvI4B7BuwOG9d8LBWi4rH3m?= =?us-ascii?Q?q7UMyE+yCqrIeC1G1OC09U+RvpTesE65hqoLxF0dFR/f5HiyPn4AkEHsl4DW?= =?us-ascii?Q?rB2CHVTurdR0vX8eB8qSoUzZVBtnj0c2mvFyuaSOgQW3AEZampMU9sAvJg2o?= =?us-ascii?Q?Chjzlr2P0iccWTET75MQeG0NG7fkKMI1CkTRWYTE?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7cd026b1-0be7-42e6-fdcc-08de101972f7 X-MS-Exchange-CrossTenant-AuthSource: SN7PR12MB8059.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Oct 2025 20:44:22.5617 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Rsrt2pYL05wRv/6D8ZQHcN3zT9/47jyaVMSt2SyWUc1bSqAVvXn4NfnOxWKK+jejb9lXnDtKUITL5WgnhpNc9w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6671 On Tue, Oct 14, 2025 at 09:43:49PM +0200, Peter Zijlstra wrote: > On Tue, Oct 14, 2025 at 01:55:47PM -0400, Joel Fernandes wrote: > > > > > > On 10/14/2025 6:48 AM, Peter Zijlstra wrote: > > > On Mon, Oct 13, 2025 at 11:48:03AM -0400, Lyude Paul wrote: > > > > > >> #define __nmi_enter() \ > > >> do { \ > > >> lockdep_off(); \ > > >> arch_nmi_enter(); \ > > >> - BUG_ON(in_nmi() == NMI_MASK); \ > > >> - __preempt_count_add(NMI_OFFSET + HARDIRQ_OFFSET); \ > > >> + BUG_ON(__this_cpu_read(nmi_nesting) == UINT_MAX); \ > > >> + __this_cpu_inc(nmi_nesting); \ > > > > > > An NMI that nests from here.. > > > > > >> + __preempt_count_add(HARDIRQ_OFFSET); \ > > >> + if (__this_cpu_read(nmi_nesting) == 1) \ > > > > > > .. until here, will see nmi_nesting > 1 and not set NMI_OFFSET. > > > > This is true, I can cure it by setting NMI_OFFSET unconditionally when > > nmi_nesting >= 1. Then the outer most NMI will then reset it. I think that will > > work. Do you see any other issue with doing so? > > unconditionally set NMI_FFSET, regardless of nmi_nesting > and only clear on exit when nmi_nesting == 0. > > Notably, when you use u64 __preempt_count, you can limit this to 32bit > only. The NMI nesting can happen in the single instruction window > between ADD and ADC. But on 64bit you don't have that gap and so don't > need to fix it. Wouldn't this break __preempt_count_dec_and_test though? If we make it 64-bit, then there is no longer a way on x86 32-bit to decrement the preempt count and zero-test the entire word in the same instruction (decl). And I feel there might be other races as well. Also this means that every preempt_disable/enable will be heavier on 32-bit. If we take the approach of this patch, but move the per-cpu counter to cache hot area, what are the other drawbacks other than few more instructions on NMI entry/exit? It feels simpler and less risky. But let me know if I missed something. thanks, - Joel