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Tue, 4 Nov 2025 08:42:46 -0800 Date: Tue, 4 Nov 2025 18:42:45 +0200 From: Zhi Wang To: Danilo Krummrich CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines Message-ID: <20251104184245.2cc7e661.zhiw@nvidia.com> In-Reply-To: References: <20251104142733.5334-1-zhiw@nvidia.com> <20251104142733.5334-5-zhiw@nvidia.com> Organization: NVIDIA X-Mailer: Claws Mail 4.3.1 (GTK 3.24.33; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|DM4PR12MB6182:EE_ X-MS-Office365-Filtering-Correlation-Id: a7d4e042-dfc0-49e1-7daa-08de1bc140fd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024|7053199007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 16:43:16.4894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7d4e042-dfc0-49e1-7daa-08de1bc140fd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6182 On Tue, 04 Nov 2025 16:41:56 +0100 "Danilo Krummrich" wrote: > On Tue Nov 4, 2025 at 3:27 PM CET, Zhi Wang wrote: > > + fn config_space(pdev: &pci::Device) -> Result { > > + let config = pdev.config_space()?; > > + > > + // TODO: use the register!() macro for defining PCI > > configuration space registers once it > > + // has been move out of nova-core. > > + dev_info!( > > + pdev.as_ref(), > > + "pci-testdev config space read8 rev ID: {:x}\n", > > + config.read8(0x8) > > + ); > > + > > + dev_info!( > > + pdev.as_ref(), > > + "pci-testdev config space read16 vendor ID: {:x}\n", > > + config.read16(0) > > + ); > > + > > + dev_info!( > > + pdev.as_ref(), > > + "pci-testdev config space read32 BAR 0: {:x}\n", > > + config.read32(0x10) > > + ); > > + > > + dev_info!( > > + pdev.as_ref(), > > + "pci-testdev config space try_read8 rev ID: {:x}\n", > > + config.try_read8(0x8)? > > + ); > > + > > + dev_info!( > > + pdev.as_ref(), > > + "pci-testdev config space try_read16 vendor ID: > > {:x}\n", > > + config.try_read16(0)? > > + ); > > + > > + dev_info!( > > + pdev.as_ref(), > > + "pci-testdev config space try_read32 BAR 0: {:x}\n", > > + config.try_read32(0x10)? > > + ); > > If we want to demonstrate the fallible accessors we should try > accesses outside the bounds of the requested config space size. > However, that doesn't really make sense, because in this case the > driver could have been calling config_space_extended() instead. > > So, I think the fallible versions don't really serve a purpose and we > should probably drop them. We can add them back if there is a use case in rust driver later. Should I arrange the traits like below? Io trait - Main trait + 32-bit access | | -- Common address/bound checks | | (accessor traits) | -- Io Fallible trait - (MMIO backend implements) | -- Io Infallible trait - (MMIO/ConfigSpace backend implements this) | | -- Io64 trait - For backend supports 64 bit access | (accessor traits) | -- Io64 Faillable trait (MMIO backend implements this) | -- Io64 Infallible trait (MMIO backend implements this) I am also thinking if we should keep 64-bit access accessor in the backend implementation instead in the Io trait (like {read, write} _relaxed), because I think few backend (PCI Config Space/I2C/SPI) would support 64-bit atomic access except MMIO backend. Z.