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Thu, 6 Nov 2025 02:28:03 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v5 0/7] rust: pci: add config space read/write support Date: Thu, 6 Nov 2025 12:27:46 +0200 Message-ID: <20251106102753.2976-1-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002325:EE_|DM4PR12MB6472:EE_ X-MS-Office365-Filtering-Correlation-Id: 452a9f92-6fe4-40f7-ab63-08de1d1f3a00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700013|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KarSjOGj9uXpHFV6n4XQ6jprA91ZHSPy0g9szqqCptu2vuV5DQb73a6HRPoA?= =?us-ascii?Q?pGHE975Vi31hsBjfiQP0CPzrPs/+KKP+tONmMqA3uGo2QWSRZyjH00/rSlUY?= =?us-ascii?Q?960eU0g8sZK5xxOVPk4yC+BmN0d4SWaVpvSOXtWvn9I4hqFCLfhA2vvyV2ZA?= =?us-ascii?Q?Az08onJCgYwJTmmWXm/LQI1Fh3Zi6/8yNmy1toP5z+70h6PV+AfK7qBkD+NH?= =?us-ascii?Q?ubkQS/NtM1fRe9JSEPc8pmi/V/OKn6AJSCL2/p7Kv0hnYSUDB7Yc0OEn2KUn?= =?us-ascii?Q?12eRGNp5+m/vkYj/Ev2wrT64Xijxd9/3a9oDP0hAgenCGhHoiNOtOQ9ms1Ao?= =?us-ascii?Q?Bpk5rB5rc4USaXzmRUF86cAoctmVc0i7zYBx0QmI5q2JCvj1kp115W8I7/6t?= =?us-ascii?Q?YvpOftw3AwStHaLWyapTVbruw55tZuTiEaVmTSXHUXDoNEAPcWmChv0RN6Pz?= =?us-ascii?Q?dJpGMy7lrdzQe5bOFbExHC+l5nPKMObXXPujJC8OBzGR6Fm7jwxwNL/nA1kV?= =?us-ascii?Q?BurQ594TFZ224erbRlkU/lf75YxSWdJ4eW2tbonKHErw6IczN6hOitewiZf1?= =?us-ascii?Q?5NtRPGVpsy6mjGCqf+o78PNFvB/mCZPKWx3hxfQzEO9VOuw9ZvsE4ZDPpJIP?= =?us-ascii?Q?urYd5+sy/CCwVoppqQZvZxXem27URJ999k/qdgDOJuPbMfzLA+QWkrC2O7rM?= =?us-ascii?Q?pyCNJuz8LerSF2GOYoUIgj4Cgo9a+YZxkRBAJjfAEs7KyRVc/cf41qckNthm?= =?us-ascii?Q?BNYUpdAvxTe3WRaFTdvj1Q4Wgh2nQgUObAv5QwzQNaIB3Z5JBBmmWThojKaH?= =?us-ascii?Q?tEQlCU7kyB7we5vyIxe/hG4KBH08ci9+qye9wYAFPMTWbfO8UzvcxjelsDwp?= =?us-ascii?Q?g+C+cZo1+4+YxAhZW4Tre0sqiPBoCGboWMMI/N3i+a45uTeFkXSzRo7eBQIE?= =?us-ascii?Q?5WajCsXC98XIqEqH8czyMFAQyv3IYY+jNfgnjQO3YY2NyUy6Ice1vkC5iGsl?= =?us-ascii?Q?EK78df03eRhlEq1RFAqD6Z4CzgZmCQQYx6RGxV/gX449kllis7eFVNkCms3K?= =?us-ascii?Q?+WJqKZAvzzUYBO1oDTT+2Z5lt2xJRsekojCg5XscU0MyeXaD7mpBh0yLqTAp?= =?us-ascii?Q?PYioI/zs04/91G+nBojpZBtmI4L113xRPKr0vMqC0N4Bv+7KOffsiKojJVBz?= =?us-ascii?Q?MRXfAi6wYuHx7TXH1ueX2utL3tRKRmaj715/BLAz1+W/K7c7d8TlqkDiOuJe?= =?us-ascii?Q?BUYd0n9CaikyPk04TLRUMrmsm6uMnCjQuNY0H+glGqTbTJTHuBo6TnETLQbc?= =?us-ascii?Q?00LhWjNlWOmIEDWe7TaW52b2tp2iPtMgUMbI6+NMdR+dz8YwEcMDMy4Szsr7?= =?us-ascii?Q?4kA4738WziCniqjeuP7gnBi5UG04iwhdC7QjIcFFJFvwnh2WbfnUxqbxjCGr?= =?us-ascii?Q?D3Y6wodwH/X6YAxPHwx35lLZEjCg8Odcw2NjEHrN0mjaoYOHkrxw25XbNb/A?= =?us-ascii?Q?FyXqHA6cMZdM7rOBGJLNw6z4X8NXVsQV2xotB1dpVSQXa0toVeVhylKvE6vX?= =?us-ascii?Q?COC0SLGdfDzIlyTl5ao=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 10:28:28.7192 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 452a9f92-6fe4-40f7-ab63-08de1d1f3a00 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002325.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6472 In the NVIDIA vGPU RFC [1], the PCI configuration space access is required in nova-core for preparing gspVFInfo when vGPU support is enabled. This series is the following up of the discussion with Danilo for how to introduce support of PCI configuration space access in Rust PCI abstractions. v5: - Remove fallible accessors of PCI configuration space. (Danilo) - Add #[repr(usize)] for enum ConfigSpace. (Danilo) - Refine the handling of return value in read accessors. (Danilo) - Add debug_assert!() in pdev::cfg_size(). (Danilo) - Add ConfigSpace.as_raw() for extracting the raw value. (Danilo) - Rebase the patches on top of driver-core-testing branch. - Convert imports touched by this series to vertical style. v4: - Refactor the SIZE constant to be an associated constant. (Alice) - Remove the default method implementations in the Io trait. (Alice) - Make cfg_size() private. (Danilo/Bjorn) - Implement the infallible accessors of ConfigSpace. (Danilo) - Create a new Io64 trait specifically for 64-bit accessors. (Danilo) - Provide two separate methods for driver: config_space() and config_space_extended(). (Danilo) - Update the sample driver to test the infallible accessors. (Danilo) v3: - Turn offset_valid() into a private function of kernel::io:Io. (Alex) - Separate try and non-try variants. (Danilo) - Move all the {try_}{read,write}{8,16,32,64} accessors to the I/O trait. (Danilo) - Replace the hardcoded MMIO type constraint with a generic trait bound so that register! macro can be used in other places. (Danilo) - Fix doctest. (John) - Add an enum for PCI configuration space size. (Danilo) - Refine the patch comments. (Bjorn) v2: - Factor out common trait as 'Io' and keep the rest routines in original 'Io' as 'Mmio'. (Danilo) - Rename 'IoRaw' to 'MmioRaw'. Update the bus MMIO implementation to use 'MmioRaw'. - Introduce pci::Device::config_space(). (Danilo) - Implement both infallible and fallible read/write routines, the device driver decicdes which version should be used. This ideas of this series are: - Factor out common traits for other accessors to share the same compiling/runtime check like before. - Factor the MMIO read/write macros from the define_read! and define_write! macros. Thus, define_{read, write}! can be used in other backends. In detail: * Introduce `call_mmio_read!` and `call_mmio_write!` helper macros to encapsulate the unsafe FFI calls. * Update `define_read!` and `define_write!` macros to delegate to the call macros. * Export `define_read` and `define_write` so they can be reused for other I/O backends (e.g. PCI config space). - Implement the PCI configuration space access backend in PCI abstractions. - Add tests for config space routines in rust PCI sample driver. [1] https://lore.kernel.org/all/20250903221111.3866249-1-zhiw@nvidia.com/ Zhi Wang (7): samples: rust: rust_driver_pci: use "kernel vertical" style for imports rust: devres: style for imports rust: io: style for imports rust: io: factor common I/O helpers into Io trait rust: io: factor out MMIO read/write macros rust: pci: add config space read/write support sample: rust: pci: add tests for config space routines drivers/gpu/nova-core/regs/macros.rs | 90 +++++--- drivers/gpu/nova-core/vbios.rs | 1 + rust/kernel/devres.rs | 34 ++- rust/kernel/io.rs | 323 ++++++++++++++++++++------- rust/kernel/io/mem.rs | 16 +- rust/kernel/io/poll.rs | 8 +- rust/kernel/pci.rs | 55 ++++- rust/kernel/pci/io.rs | 72 +++++- samples/rust/rust_driver_pci.rs | 38 +++- 9 files changed, 496 insertions(+), 141 deletions(-) -- 2.51.0