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Thu, 6 Nov 2025 09:43:42 -0800 Date: Thu, 6 Nov 2025 19:43:40 +0200 From: Zhi Wang To: Danilo Krummrich CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v5 6/7] rust: pci: add config space read/write support Message-ID: <20251106194340.4e8aa79a.zhiw@nvidia.com> In-Reply-To: References: <20251106102753.2976-1-zhiw@nvidia.com> <20251106102753.2976-7-zhiw@nvidia.com> Organization: NVIDIA X-Mailer: Claws Mail 4.3.1 (GTK 3.24.33; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE4:EE_|LV2PR12MB5872:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e5849cd-6a2f-4120-56ff-08de1d5c17a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013|7053199007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2025 17:44:10.2517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e5849cd-6a2f-4120-56ff-08de1d5c17a3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5872 On Thu, 6 Nov 2025 17:30:39 +0100 Danilo Krummrich wrote: > > impl Device { > > @@ -441,6 +480,20 @@ pub fn set_master(&self) { > > // SAFETY: `self.as_raw` is guaranteed to be a pointer to > > a valid `struct pci_dev`. unsafe { > > bindings::pci_set_master(self.as_raw()) }; } > > + > > + /// Return an initialized config space object. > > + pub fn config_space<'a>( > > + &'a self, > > + ) -> Result > }>> { > > + Ok(ConfigSpace { pdev: self }) > > + } > > + > > + /// Return an initialized config space object. > > + pub fn config_space_exteneded<'a>( > > + &'a self, > > + ) -> Result > ConfigSpaceSize::Extended.as_raw() }>> { > > + Ok(ConfigSpace { pdev: self }) > > + } > > } > > Please implement them for Device rather than Device. > Also, the methods seem to be infallible, hence no need to return a > Result. > Oops, I missed this one during the rebase. Will fix it in the next spin. Thanks for catching this. > > +/// Represents the PCI configuration space of a device. > > +/// > > +/// Provides typed read and write accessors for configuration > > registers +/// using the standard `pci_read_config_*` and > > `pci_write_config_*` helpers. +/// > > +/// The generic const parameter `SIZE` can be used to indicate the > > +/// maximum size of the configuration space (e.g. 256 bytes for > > legacy, +/// 4096 bytes for extended config space). The actual size > > is obtained +/// from the underlying `struct pci_dev` via > > [`Device::cfg_size`]. +pub struct ConfigSpace<'a, const SIZE: usize > > = { ConfigSpaceSize::Extended as usize }> { > > + pub(crate) pdev: &'a Device, > > /Core/Bound/