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Mon, 17 Nov 2025 12:28:07 -0800 Date: Mon, 17 Nov 2025 22:28:06 +0200 From: Zhi Wang To: Joel Fernandes CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v6 RESEND 6/7] rust: pci: add config space read/write support Message-ID: <20251117222806.49d1a13d.zhiw@nvidia.com> In-Reply-To: <20251114002005.GA2384907@joelbox2> References: <20251110204119.18351-1-zhiw@nvidia.com> <20251110204119.18351-7-zhiw@nvidia.com> <20251114002005.GA2384907@joelbox2> Organization: NVIDIA X-Mailer: Claws Mail 4.3.1 (GTK 3.24.33; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009B:EE_|DS4PR12MB9682:EE_ X-MS-Office365-Filtering-Correlation-Id: 11f730a7-871a-4139-467e-08de2617e059 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 20:28:32.1889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 11f730a7-871a-4139-467e-08de2617e059 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9682 On Thu, 13 Nov 2025 19:20:05 -0500 Joel Fernandes wrote: > Hi Zhi, > > On Mon, Nov 10, 2025 at 10:41:18PM +0200, Zhi Wang wrote: > [..] > > impl Device { > > diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs > > index 2bbb3261198d..bb78a83fe92c 100644 > > --- a/rust/kernel/pci/io.rs > > +++ b/rust/kernel/pci/io.rs > > @@ -2,12 +2,19 @@ > > > > //! PCI memory-mapped I/O infrastructure. > > > > -use super::Device; > > +use super::{ > > + ConfigSpaceSize, > > + Device, // > > +}; > > use crate::{ > > bindings, > > device, > > devres::Devres, > > io::{ > > + define_read, > > + define_write, > > + Io, > > + IoInfallible, > > Mmio, > > MmioRaw, // > > }, > > @@ -16,6 +23,58 @@ > > }; > > use core::ops::Deref; > > > > +/// The PCI configuration space of a device. > > +/// > > +/// Provides typed read and write accessors for configuration > > registers +/// using the standard `pci_read_config_*` and > > `pci_write_config_*` helpers. +/// > > +/// The generic const parameter `SIZE` can be used to indicate the > > +/// maximum size of the configuration space (e.g. 256 bytes for > > legacy, +/// 4096 bytes for extended config space). > > +pub struct ConfigSpace<'a, const SIZE: usize = { > > ConfigSpaceSize::Extended as usize }> { > > + pub(crate) pdev: &'a Device, > > +} > > + > > +macro_rules! call_config_read { > > + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) => > > {{ > > + let mut val: $ty = 0; > > + let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), > > $addr as i32, &mut val) }; > > + val > > + }}; > > +} > > + > > +macro_rules! call_config_write { > > + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, > > $value:expr) => { > > + let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), > > $addr as i32, $value) }; > > unsafe block needs safety comments, also I understand 'as' to convert snip > is generally forbidden without a CAST: comment or using ::from() for > conversion because it can by a lossy conversion. > Let me take a look, basically this was similar with the define_{read, mmio} macros, which has originally been from the mainline. Might have to fix that part as well. > Also we should have a comment on why its safe for _ret to be ignored. > Basically what guarantees that the call is really infallible? > Anything we can do to ensure errors are not silently ignored? Let me > know if I missed something. > This was discussed with Danilo on Zulip. The driver will observe a !0 value on read when an error occurs in the infallible accessors. For writes, I think the driver should read the value back. (similar with MMIO cases) Besides those, I think the driver needs to use fallible ones if it really cares about the return. Z. > [..] > > > + > > + /// Return an initialized config space object. > > + pub fn config_space_exteneded<'a>( > > typo in func name. > > thanks, > > - Joel > > > + &'a self, > > + ) -> Result > ConfigSpaceSize::Extended.as_raw() }>> { > > + Ok(ConfigSpace { pdev: self }) > > + } > > } > > -- > > 2.51.0 > >