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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF0002636E.mail.protection.outlook.com (10.167.241.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9388.8 via Frontend Transport; Mon, 1 Dec 2025 23:41:18 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 1 Dec 2025 15:41:01 -0800 Received: from ttabi.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 1 Dec 2025 15:41:00 -0800 From: Timur Tabi To: Danilo Krummrich , Alexandre Courbot , Lyude Paul , Joel Fernandes , John Hubbard , , Subject: [PATCH v2 01/13] gpu: nova-core: rename Imem to ImemSecure Date: Mon, 1 Dec 2025 17:39:10 -0600 Message-ID: <20251201233922.27218-2-ttabi@nvidia.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251201233922.27218-1-ttabi@nvidia.com> References: <20251201233922.27218-1-ttabi@nvidia.com> Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636E:EE_|CH2PR12MB4312:EE_ X-MS-Office365-Filtering-Correlation-Id: 1d4a9ef4-65eb-47d3-8845-08de31331ffc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2025 23:41:18.1351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d4a9ef4-65eb-47d3-8845-08de31331ffc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4312 Rename FalconMem::Imem to ImemSecure to indicate that it references Secure Instruction Memory. This change has no functional impact. On Falcon cores, pages in instruction memory can be tagged as Secure or Non-Secure. For GA102 and later, only Secure is used, which is why FalconMem::Imem seems appropriate. However, Turing firmware images can also contain non-secure sections, and so FalconMem needs to support that. By renaming Imem to ImemSec now, future patches for Turing support will be simpler. Nouveau uses the term "IMEM" to refer both to the Instruction Memory block on Falcon cores as well as to the images of secure firmware uploaded to part of IMEM. OpenRM uses the terms "ImemSec" and "ImemNs" instead, and uses "IMEM" just to refer to the physical memory device. Renaming these terms allows us to align with OpenRM, avoid confusion between IMEM and ImemSec, and makes future patches simpler. Signed-off-by: Timur Tabi --- drivers/gpu/nova-core/falcon.rs | 14 +++++++------- drivers/gpu/nova-core/firmware/booter.rs | 12 ++++++------ drivers/gpu/nova-core/firmware/fwsec.rs | 2 +- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 82c661aef594..618e3962d83a 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -237,8 +237,8 @@ fn from(value: PeregrineCoreSelect) -> Self { /// Different types of memory present in a falcon core. #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub(crate) enum FalconMem { - /// Instruction Memory. - Imem, + /// Secure Instruction Memory. + ImemSecure, /// Data Memory. Dmem, } @@ -345,8 +345,8 @@ pub(crate) struct FalconBromParams { /// Trait for providing load parameters of falcon firmwares. pub(crate) trait FalconLoadParams { - /// Returns the load parameters for `IMEM`. - fn imem_load_params(&self) -> FalconLoadTarget; + /// Returns the load parameters for Secure `IMEM`. + fn imem_sec_load_params(&self) -> FalconLoadTarget; /// Returns the load parameters for `DMEM`. fn dmem_load_params(&self) -> FalconLoadTarget; @@ -457,7 +457,7 @@ fn dma_wr>( // // For DMEM we can fold the start offset into the DMA handle. let (src_start, dma_start) = match target_mem { - FalconMem::Imem => (load_offsets.src_start, fw.dma_handle()), + FalconMem::ImemSecure => (load_offsets.src_start, fw.dma_handle()), FalconMem::Dmem => ( 0, fw.dma_handle_with_offset(load_offsets.src_start.into_safe_cast())?, @@ -508,7 +508,7 @@ fn dma_wr>( let cmd = regs::NV_PFALCON_FALCON_DMATRFCMD::default() .set_size(DmaTrfCmdSize::Size256B) - .set_imem(target_mem == FalconMem::Imem) + .set_imem(target_mem == FalconMem::ImemSecure) .set_sec(if sec { 1 } else { 0 }); for pos in (0..num_transfers).map(|i| i * DMA_LEN) { @@ -543,7 +543,7 @@ pub(crate) fn dma_load>(&self, bar: &Bar0, fw: &F) .set_mem_type(FalconFbifMemType::Physical) }); - self.dma_wr(bar, fw, FalconMem::Imem, fw.imem_load_params(), true)?; + self.dma_wr(bar, fw, FalconMem::ImemSecure, fw.imem_sec_load_params(), true)?; self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params(), true)?; self.hal.program_brom(self, bar, &fw.brom_params())?; diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-core/firmware/booter.rs index f107f753214a..096cd01dbc9d 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -251,8 +251,8 @@ impl<'a> FirmwareSignature for BooterSignature<'a> {} /// The `Booter` loader firmware, responsible for loading the GSP. pub(crate) struct BooterFirmware { - // Load parameters for `IMEM` falcon memory. - imem_load_target: FalconLoadTarget, + // Load parameters for Secure `IMEM` falcon memory. + imem_sec_load_target: FalconLoadTarget, // Load parameters for `DMEM` falcon memory. dmem_load_target: FalconLoadTarget, // BROM falcon parameters. @@ -354,7 +354,7 @@ pub(crate) fn new( }; Ok(Self { - imem_load_target: FalconLoadTarget { + imem_sec_load_target: FalconLoadTarget { src_start: app0.offset, dst_start: 0, len: app0.len, @@ -371,8 +371,8 @@ pub(crate) fn new( } impl FalconLoadParams for BooterFirmware { - fn imem_load_params(&self) -> FalconLoadTarget { - self.imem_load_target.clone() + fn imem_sec_load_params(&self) -> FalconLoadTarget { + self.imem_sec_load_target.clone() } fn dmem_load_params(&self) -> FalconLoadTarget { @@ -384,7 +384,7 @@ fn brom_params(&self) -> FalconBromParams { } fn boot_addr(&self) -> u32 { - self.imem_load_target.src_start + self.imem_sec_load_target.src_start } } diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-core/firmware/fwsec.rs index b28e34d279f4..6a2f5a0d4b15 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -224,7 +224,7 @@ pub(crate) struct FwsecFirmware { } impl FalconLoadParams for FwsecFirmware { - fn imem_load_params(&self) -> FalconLoadTarget { + fn imem_sec_load_params(&self) -> FalconLoadTarget { FalconLoadTarget { src_start: 0, dst_start: self.desc.imem_phys_base, -- 2.52.0