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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2025 23:41:15.2759 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b69c0a0-cf92-476f-ef2b-08de31331e45 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017094.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7711 The GSP booter firmware in Turing and GA100 includes a third memory section called ImemNonSecure, which is non-secure IMEM. This section must be loaded separately from DMEM and secure IMEM, but only if it actually exists. Signed-off-by: Timur Tabi --- drivers/gpu/nova-core/falcon.rs | 21 +++++++++++++++++++-- drivers/gpu/nova-core/firmware/booter.rs | 9 +++++++++ drivers/gpu/nova-core/firmware/fwsec.rs | 5 +++++ 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 618e3962d83a..fed597a29fa4 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -239,6 +239,8 @@ fn from(value: PeregrineCoreSelect) -> Self { pub(crate) enum FalconMem { /// Secure Instruction Memory. ImemSecure, + /// Non-Secure Instruction Memory. + ImemNonSecure, /// Data Memory. Dmem, } @@ -348,6 +350,10 @@ pub(crate) trait FalconLoadParams { /// Returns the load parameters for Secure `IMEM`. fn imem_sec_load_params(&self) -> FalconLoadTarget; + /// Returns the load parameters for Non-Secure `IMEM`, + /// used only on Turing and GA100. + fn imem_ns_load_params(&self) -> Option; + /// Returns the load parameters for `DMEM`. fn dmem_load_params(&self) -> FalconLoadTarget; @@ -457,7 +463,10 @@ fn dma_wr>( // // For DMEM we can fold the start offset into the DMA handle. let (src_start, dma_start) = match target_mem { - FalconMem::ImemSecure => (load_offsets.src_start, fw.dma_handle()), + FalconMem::ImemSecure | FalconMem::ImemNonSecure => ( + load_offsets.src_start, + fw.dma_handle() + ), FalconMem::Dmem => ( 0, fw.dma_handle_with_offset(load_offsets.src_start.into_safe_cast())?, @@ -508,7 +517,7 @@ fn dma_wr>( let cmd = regs::NV_PFALCON_FALCON_DMATRFCMD::default() .set_size(DmaTrfCmdSize::Size256B) - .set_imem(target_mem == FalconMem::ImemSecure) + .set_imem(target_mem != FalconMem::Dmem) .set_sec(if sec { 1 } else { 0 }); for pos in (0..num_transfers).map(|i| i * DMA_LEN) { @@ -546,6 +555,14 @@ pub(crate) fn dma_load>(&self, bar: &Bar0, fw: &F) self.dma_wr(bar, fw, FalconMem::ImemSecure, fw.imem_sec_load_params(), true)?; self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params(), true)?; + if let Some(nmem) = fw.imem_ns_load_params() { + // This code should never actual get executed, because the Non-Secure + // section only exists on firmware used by Turing and GA100, and + // those platforms do not use DMA. But we include this code for + // consistency. + self.dma_wr(bar, fw, FalconMem::ImemNonSecure, nmem, false)?; + } + self.hal.program_brom(self, bar, &fw.brom_params())?; // Set `BootVec` to start of non-secure code. diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-core/firmware/booter.rs index 096cd01dbc9d..1b98bb47424c 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -253,6 +253,9 @@ impl<'a> FirmwareSignature for BooterSignature<'a> {} pub(crate) struct BooterFirmware { // Load parameters for Secure `IMEM` falcon memory. imem_sec_load_target: FalconLoadTarget, + // Load parameters for Non-Secure `IMEM` falcon memory, + // used only on Turing and GA100 + imem_ns_load_target: Option, // Load parameters for `DMEM` falcon memory. dmem_load_target: FalconLoadTarget, // BROM falcon parameters. @@ -359,6 +362,8 @@ pub(crate) fn new( dst_start: 0, len: app0.len, }, + // Exists only in the booter image for Turing and GA100 + imem_ns_load_target: None, dmem_load_target: FalconLoadTarget { src_start: load_hdr.os_data_offset, dst_start: 0, @@ -375,6 +380,10 @@ fn imem_sec_load_params(&self) -> FalconLoadTarget { self.imem_sec_load_target.clone() } + fn imem_ns_load_params(&self) -> Option { + self.imem_ns_load_target.clone() + } + fn dmem_load_params(&self) -> FalconLoadTarget { self.dmem_load_target.clone() } diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-core/firmware/fwsec.rs index 6a2f5a0d4b15..e4009faba6c5 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -232,6 +232,11 @@ fn imem_sec_load_params(&self) -> FalconLoadTarget { } } + fn imem_ns_load_params(&self) -> Option { + // Only used on Turing and GA100, so return None for now + None + } + fn dmem_load_params(&self) -> FalconLoadTarget { FalconLoadTarget { src_start: self.desc.imem_load_size, -- 2.52.0