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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2025 23:41:22.8987 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8775bb2e-00d5-4c60-aa6a-08de313322d0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4346 Define some more GPU registers used to boot GSP-RM on Turing and GA100. Signed-off-by: Timur Tabi --- drivers/gpu/nova-core/regs.rs | 63 +++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 88bec1d4830b..2143869d27ba 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -258,6 +258,11 @@ pub(crate) fn vga_workspace_addr(self) -> Option { 6:6 swgen0 as bool; }); +// Interrupt mask clear register. Writing 1 to a bit clears the corresponding interrupt mask. +register!(NV_PFALCON_FALCON_IRQMCLR @ PFalconBase[0x00000014] { + 31:0 value as u32; +}); + register!(NV_PFALCON_FALCON_MAILBOX0 @ PFalconBase[0x00000040] { 31:0 value as u32; }); @@ -266,6 +271,14 @@ pub(crate) fn vga_workspace_addr(self) -> Option { 31:0 value as u32; }); +// Interface enable register. +register!(NV_PFALCON_FALCON_ITFEN @ PFalconBase[0x00000048] { + 0:0 ctxen as bool, "Context interface enable"; + 1:1 mthden as bool, "Method interface enable"; + 2:2 postwr as bool; + 4:4 secwl_cpuctl_alias as bool; +}); + // Used to store version information about the firmware running // on the Falcon processor. register!(NV_PFALCON_FALCON_OS @ PFalconBase[0x00000080] { @@ -307,6 +320,13 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 7:7 secure_stat as bool; }); +impl NV_PFALCON_FALCON_DMACTL { + /// Returns `true` if memory scrubbing is completed. + pub(crate) fn mem_scrubbing_done(self) -> bool { + !self.dmem_scrubbing() && !self.imem_scrubbing() + } +} + register!(NV_PFALCON_FALCON_DMATRFBASE @ PFalconBase[0x00000110] { 31:0 base as u32; }); @@ -353,6 +373,42 @@ pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { 1:1 startcpu as bool; }); +// Config memory base address. Specifies the upper address bits that must be matched +// to access the config aperture. The base may not be zero as that would conflict with DMEM. +register!(NV_PFALCON2_FALCON_CMEMBASE @ PFalcon2Base[0x00000160] { + 31:18 value as u16; +}); + +// IMEM access control register. Up to 4 ports are available for IMEM access. +register!(NV_PFALCON_FALCON_IMEMC @ PFalconBase[0x00000180[4; 16]] { + 15:0 offs as u16, "IMEM block and word offset"; + 24:24 aincw as bool, "Auto-increment on write"; + 28:28 secure as bool, "Access secure IMEM"; +}); + +// IMEM data register. Reading/writing this register accesses IMEM at the address +// specified by the corresponding IMEMC register. +register!(NV_PFALCON_FALCON_IMEMD @ PFalconBase[0x00000184[4; 16]] { + 31:0 data as u32; +}); + +// IMEM tag register. Used to set the tag for the current IMEM block. +register!(NV_PFALCON_FALCON_IMEMT @ PFalconBase[0x00000188[4; 16]] { + 15:0 tag as u16; +}); + +// DMEM access control register. Up to 8 ports are available for DMEM access. +register!(NV_PFALCON_FALCON_DMEMC @ PFalconBase[0x000001c0[8; 8]] { + 15:0 offs as u16, "DMEM block and word offset"; + 24:24 aincw as bool, "Auto-increment on write"; +}); + +// DMEM data register. Reading/writing this register accesses DMEM at the address +// specified by the corresponding DMEMC register. +register!(NV_PFALCON_FALCON_DMEMD @ PFalconBase[0x000001c4[8; 8]] { + 31:0 data as u32; +}); + // Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` depending on the falcon // instance. register!(NV_PFALCON_FALCON_ENGINE @ PFalconBase[0x000003c0] { @@ -390,6 +446,13 @@ pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { // PRISCV +// RISC-V status register for debug (Turing and GA100 only). +// Reflects current RISC-V core status. +register!(NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS @ PFalcon2Base[0x00000240] { + 0:0 active_stat as bool, "RISC-V core active/inactive status"; +}); + +// GA102 and later register!(NV_PRISCV_RISCV_CPUCTL @ PFalcon2Base[0x00000388] { 0:0 halted as bool; 7:7 active_stat as bool; -- 2.52.0